CD4066B CMOS QUAD BILATERAL SWITCH
SCHS051D NOVEMBER 1998 REVISED SEPTEMBER 2003
D 15-V Digital or 7.5-V Peak-to-Peak D D D D D D
Switching 125- Typical On-State Resistance for 15-V Operation Switch On-State Resistance Matched to Within 5 Over 15-V Signal-Input Range On-State Resistance Flat Over Full Peak-to-Peak Signal Range High On/Off Output-Voltage Ratio: 80 dB Typical at fis = 10 kHz, RL = 1 k High Degree of Linearity: <0.5% Distortion Typical at fis = 1 kHz, Vis = 5 V p-p, VDD VSS 10 V, RL = 10 k Extremely Low Off-State Switch Leakage, Resulting in Very Low Offset Current and High Effective Off-State Resistance: 10 pA Typical at VDD VSS = 10 V, TA = 25C Extremely High Control Input Impedance (Control Circuit Isolated From Signal Circuit): 1012 Typical Low Crosstalk Between Switches: 50 dB Typical at fis = 8 MHz, RL = 1 k
D Matched Control-Input to Signal-Output D D D D
Capacitance: Reduces Output Signal Transients Frequency Response, Switch On = 40 MHz Typical 100% Tested for Quiescent Current at 20 V 5-V, 10-V, and 15-V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard No. 13-B, Standard Specifications for Description of B Series CMOS Devices Applications: Analog Signal Switching/Multiplexing: Signal Gating, Modulator, Squelch Control, Demodulator, Chopper, Commutating Switch Digital Signal Switching/Multiplexing Transmission-Gate Logic Implementation Analog-to-Digital and Digital-to-Analog Conversion Digital Control of Frequency, Impedance, Phase, and Analog-Signal Gain
E, F, M, NS, OR PW PACKAGE (TOP VIEW)
SIG A IN/OUT SIG A OUT/IN SIG B OUT/IN SIG B IN/OUT CONTROL B CONTROL C VSS
VDD CONTROL A CONTROL D SIG D IN/OUT SIG D OUT/IN SIG C OUT/IN SIG C IN/OUT
description/ordering information
The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range. The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and, thus, keeps the on-state resistance low over the full operating-signal range. The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold applications, the CD4016B is recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2003, Texas Instruments Incorporated

POST OFFICE BOX 655303

DALLAS, TEXAS 75265
description/ordering information (continued)

ORDERING INFORMATION

TA CDIP F PDIP E PACKAGE Tube of 25 Tube of 25 Tube of 50 55C to 125C SOIC M SOP NS TSSOP PW Reel of 2500 Reel of 250 Reel of 2000 Tube of 90 Reel of 2000 ORDERABLE PART NUMBER CD4066BF3A CD4066BE CD4066BM CD4066BM96 CD4066BMT CD4066BNSR CD4066BPW CD4066BPWR CD4066B CM066B CD4066BM TOP-SIDE MARKING CD4066BF3A CD4066BE
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Switch Control In Vis

Out Vos

Control VC

VSS VDD

VSS All control inputs are protected by the CMOS protection network. NOTES: A. All p substrates are connected to VDD. B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS C. Signal-level range: VSS Vis VDD

92CS-29113

Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
DC supply-voltage range, VDD (voltages referenced to VSS terminal). 0.5 V to 20 V Input voltage range, Vis (all inputs). 0.5 V to VDD + 0.5 V DC input current, IIN (any one input). 10 mA Package thermal impedance, JA (see Note 1): E package. 80C/W M package. 86C/W NS package. 76C/W PW package. 113C/W Lead temperature (during soldering): At distance 1/16 1/32 inch (1,59 0,79 mm) from case for 10 s max. 265C Storage temperature range, Tstg. 65C to 150C

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN VDD TA Supply voltage Operating free-air temperature MAX UNIT V C
electrical characteristics
LIMITS AT INDICATED TEMPERATURES PARAMETER TEST CONDITIONS VIN (V) 0, 5 IDD Quiescent device current 0, 10 0, 15 0, 20 Signal Inputs (Vis) and Outputs (Vos) VC = VDD, RL = 10 k returned V DD * V SS to , 2 Vis = VSS to VDD On-state resistance difference between any two switches Total harmonic distortion 3-dB cutoff frequency (switch on) 50-dB feedthrough frequency (switch off) Iis Input/output leakage current (switch off) (max) 50-dB crosstalk frequency RL = 10 k, VC = VDD VC = VDD = 5 V, VSS = 5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 10 k, fis = 1-kHz sine wave VC = VDD = 5 V, VSS = 5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 1 k VC = VSS = 5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 1 k VC = 0 V, Vis = 18 V, Vos = 0 V; and VC = 0 V, Vis = 0 V, Vos = 18 V VC(A) = VDD = 5 V, VC(B) = VSS = 5 V, Vis(A) = 5 Vp-p, 50- source, RL = 1 k RL = 200 k, VC = VDD, VSS = GND, CL = 50 pF, Vis = 10 V (square wave centered on 5 V), tr, tf = 20 ns VDD = 5 V, VC = VSS = 5 V VDD = 5 V, VC = VSS = 5 V VDD = 5 V, VC = VSS = 5 V 18 0.1 0.5 0.4 % 240 VDD (V) 25C 55C 0.25 0.5 40C 0.25 0.5 85C 7.125C 7.TYP 0.01 0.01 0.01 0.02 MAX 0.25 0.5 A A UNIT
On-state resistance (max)

15 pF pF pF ns

Propagation delay (signal input to signal output) Input capacitance Output capacitance Feedthrough

Cis Cos Cios

electrical characteristics (continued)
LIMITS AT INDICATED TEMPERATURES CHARACTERISTIC Control (VC) VILC Control input, low voltage (max) |Iis| < 10 A, Vis = VSS, VOS = VDD, and Vis = VDD, VOS = VSS VIHC Control input, high voltage Input current (max) Crosstalk (control input to signal output) Turn-on and turn-off propagation delay See Figure 6 Vis VDD, VDD VSS = 18 V, VCC VDD VSS VC = 10 V (square wave), tr, tf = 20 ns, RL = 10 k VIN = VDD, tr, tf = 20 ns, CL = 50 pF, RL = 1 k Vis = VDD, VSS = GND, RL = 1 k to GND, CL = 50 pF, VC = 10 V (square wave centered on 5 V), tr, tf = 20 ns, Vos = 1/2 Vos at 1 kHz IIN 0.1 0.3.5 (MIN) 7 (MIN) 11 (MIN) 9 9.7.5 pF MHz 30 ns 0.1 A mV V V TEST CONDITIONS VDD (V) 25C 55C 40C 85C 125C TYP MAX UNIT

Maximum control input repetition rate

Input capacitance

switching characteristics
SWITCH INPUT VDD (V) Vis (V) Iis (mA) 55C 0.64 0.64 1.6 1.6 4.2 4.2 40C 0.61 0.61 1.5 1.4 25C 0.51 0.51 1.3 1.3 3.4 3.4 85C 0.42 0.42 1.1 1.1 2.8 2.8 125C 0.36 0.36 0.9 0.9 2.4 2.4 13.5 9.5 1.5 4.6 0.5 SWITCH OUTPUT, Vos (V) MIN MAX 0.4

TYPICAL CHARACTERISTICS

TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)
r Channel On-State Resistance on +25C 200 55C 4 Supply Voltage (VDD VSS) = 5 V TA = 125C r Channel On-State Resistance on 200 +25C 150 55C 7.2.2.7.5 10
Supply Voltage (VDD VSS) = 10 V TA = 125C
Vis Input Signal Voltage V

92CS-27326RI

92CS-27327RI

Figure 2

r Channel On-State Resistance on r Channel On-State Resistance on Supply Voltage (VDD VSS) = 15 V 200 TA = 125C 10 7.2.2.7.Vis Input Signal Voltage V

92CS-27329RI

Figure 3
TA = 125C V 10 7.2.2.7.15 V Supply Voltage (VDD VSS) = 5 V

+25C 55C

92CS-27330RI

Figure 4

Figure 5
Vis Iis CD4066B 1 of 4 Switches |Vis Vos| |Iis|

92CS-30966

Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification
VDD TG On Keithley 160 Digital Multimeter 1-k Range
Y X-Y Plotter X H. P. Moseley 7030A

92CS-22716

Figure 7. Channel On-State Resistance Measurement Circuit
POWER DISSIPATION PER PACKAGE vs SWITCHING FREQUENCY
104 PD Power Dissipation Per Package W 3
TYPICAL ON CHARACTERISTICS FOR 1 OF 4 CHANNELS

TA = 25C

2 VO Output Voltage V
Supply Voltage (VDD) = 15 V 10 V 5V

CD4066B 14

VC = VDD

VDD Vos RL

CD4066B 1 of 4 Switches VSS
All unused terminals are connected to VSS

VI Input Voltage V

92CS-30919
f Switching Frequency kHz

Figure 8

Figure 9

92C-30920

VC = 5 V
VDD = 5 V VDD CD4066B 1 of 4 Switches VSS

92CS-30922

CD4066B 1 of 4 Switches Cis VSS = 5 V Cos

VC = VSS Vis = VDD

92CS-30921
Measured on Boonton capacitance bridge, model 75a (1 MHz); test-fixture capacitance nulled out.
All unused terminals are connected to VSS.
Figure 10. Typical On Characteristics for One of Four Channels
VC = VDD Vis VDD CD4066B 1 of 4 Switches VSS VDD tr = tf = 20 ns

92CS-30923

Figure 11. Off-Switch Input or Output Leakage
+10 V tr = tf = 20 ns 200 k

V Vis CD4066B os 1 of 4 Switches 10 k 1 k VSS

92CS-30924

Figure 12. Propagation Delay Time Signal Input (Vis) to Signal Output (Vos)
Figure 13. Crosstalk-Control Input to Signal Output
VDD tr = tf = 20 ns VC = VDD VDD
VDD CD4066B 1 of 4 Switches VSS 50 pF Vos
NOTES: A. All unused terminals are connected to VSS. B. Delay is measured at Vos level of +10% from ground (turn-on) or on-state output level (turn-off).

92CS-30925

Figure 14. Propagation Delay, tPLH, tPHL Control-Signal Output
tr VC 10% 90% 50% Repetition Rate tr = tf = 20 ns Vos

tf 10 V 0V

V OS +

V OS at 1 kHz 2

VDD = 10 V VC Vis = 10 V CD4066B 1 of 4 Switches VSS V OS + V OS at 1 kHz 2
Figure 15. Maximum Allowable Control-Input Repetition Rate

VDD Inputs

92CS-27555
Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. Measure control inputs only.
Figure 16. Input Leakage-Current Test Circuit
Clock Reset 1 Q1 QJJJJExternal Reset Clock 1 P E J1

P E J1

CD4018B

1/4 CD4066B

1/3 CD4049B Signal Inputs 2 1/6 CD4049B 10 k 12 CD4001B 7 1/3 CD4049B 10 6

CD4001B

2 Signal Outputs

Channel 1

Channel 1 Channel 2 Channel 3 Channel 4

CD4066B

Channel 2
Package Count 2 - CD4001B 1 - CD4049B 3 - CD4066B 2 - CD4018B

Channel 3

Maximum Allowable Signal Level
VDD 30% (VDD VSS) VSS Chan 1 Chan 2 Chan 3 Chan 4

LPF Channel 4

92CM-30928
Figure 17. Four-Channel PAM Multiplex System Diagram
5V V VDD = 5 V 5V 0 IN CD4054B CD4066B SWA SWB SWC SWD Digital Control Inputs VSS = 0 V VEE = 5 V VSS = 5 V

92CS-30927

Analog Inputs (5 V) VDD = 5 V

Analog Outputs (5 V)

Figure 18. Bidirectional Signal Transmission Via Digital Control Logic

APPLICATION INFORMATION

In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load of the four CD4066B bilateral switches). This provision avoids any permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4066B. In certain applications, the external load-resistor current can include both VDD and signal-line components. To avoid drawing VDD current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the bidirectional switch must not exceed 0.8 V (calculated from ron values shown). No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10.

PACKAGE OPTION ADDENDUM

www.ti.com

7-Jun-2010

PACKAGING INFORMATION
Orderable Device CD4066BE CD4066BEE4 CD4066BF CD4066BF3A CD4066BF3AS2283 CD4066BF3AS2534 CD4066BM CD4066BM96 CD4066BM96E4 CD4066BM96G4 CD4066BME4 CD4066BMG4 CD4066BMT CD4066BMTE4 CD4066BMTG4 CD4066BNSR CD4066BNSRE4 CD4066BNSRG4 Status
Package Type Package Drawing PDIP PDIP CDIP CDIP CDIP CDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SO SO SO N N J J J J D D D D D D D D D NS NS NS

Pins 14 14

Package Qty 1 1

Eco Plan

Lead/ Ball Finish

MSL Peak Temp

Samples (Requires Login) Contact TI Distributor or Sales Office Contact TI Distributor or Sales Office Purchase Samples Purchase Samples Samples Not Available Samples Not Available Purchase Samples Contact TI Distributor or Sales Office Contact TI Distributor or Sales Office Contact TI Distributor or Sales Office Purchase Samples Purchase Samples Purchase Samples Purchase Samples Purchase Samples Contact TI Distributor or Sales Office Contact TI Distributor or Sales Office Contact TI Distributor or Sales Office
ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Pb-Free (RoHS) Pb-Free (RoHS) TBD TBD TBD TBD
CU NIPDAU N / A for Pkg Type CU NIPDAU N / A for Pkg Type A42 A42 Call TI Call TI N / A for Pkg Type N / A for Pkg Type Call TI Call TI

2000 2000

Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM

Addendum-Page 1

Orderable Device CD4066BPW CD4066BPWE4 CD4066BPWG4 CD4066BPWR CD4066BPWRE4 CD4066BPWRG4 JM38510/05852BCA

Status

Package Type Package Drawing TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP CDIP PW PW PW PW PW PW J

Pins 14

Package Qty 1
Samples (Requires Login) Purchase Samples Purchase Samples Purchase Samples Contact TI Distributor or Sales Office Contact TI Distributor or Sales Office Contact TI Distributor or Sales Office Purchase Samples

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) TBD
CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU Level-1-260C-UNLIM A42 N / A for Pkg Type
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD4066B, CD4066B-MIL :
Catalog: CD4066B Military: CD4066B-MIL
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com 9-Mar-2011

TAPE AND REEL INFORMATION
*All dimensions are nominal

Device

Package Package Pins Type Drawing SOIC SOIC SOIC SO TSSOP D D D NS PW 14
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 330.0 330.0 330.0 16.4 16.4 16.4 16.4 12.4 6.5 6.5 6.5 8.2 6.9
B0 (mm) 9.0 9.0 9.0 10.5 5.6
K0 (mm) 2.1 2.1 2.1 2.5 1.6
P1 (mm) 8.0 8.0 8.0 12.0 8.0
W Pin1 (mm) Quadrant 16.0 16.0 16.0 16.0 12.0 Q1 Q1 Q1 Q1 Q1
CD4066BM96 CD4066BM96 CD4066BMT CD4066BNSR CD4066BPWR

Pack Materials-Page 1

Device CD4066BM96 CD4066BM96 CD4066BMT CD4066BNSR CD4066BPWR
Package Type SOIC SOIC SOIC SO TSSOP
Package Drawing D D D NS PW

SPQ 2000

Length (mm) 333.2 346.0 346.0 346.0 346.0
Width (mm) 345.9 346.0 346.0 346.0 346.0
Height (mm) 28.6 33.0 33.0 33.0 29.0

Pack Materials-Page 2

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright 2011, Texas Instruments Incorporated

CD4066BQ1 CMOS QUAD BILATERAL SWITCH

SCHS352 JANUARY 2004

D Qualification in Accordance With D D D D D D D D D
AEC-Q100 Qualified for Automotive Applications Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval 15-V Digital or 7.5-V Peak-to-Peak Switching 125- Typical On-State Resistance for 15-V Operation Switch On-State Resistance Matched to Within 5 Over 15-V Signal-Input Range On-State Resistance Flat Over Full Peak-to-Peak Signal Range High On/Off Output-Voltage Ratio: 80 dB Typical at fis = 10 kHz, RL = 1 k High Degree of Linearity: <0.5% Distortion Typical at fis = 1 kHz, Vis = 5 V p-p, VDD VSS 10 V, RL = 10 k Extremely Low Off-State Switch Leakage, Resulting in Very Low Offset Current and High Effective Off-State Resistance: 10 pA Typical at VDD VSS = 10 V, TA = 25C
D Extremely High Control Input Impedance D D D D D D
(Control Circuit Isolated From Signal Circuit): 1012 Typical Low Crosstalk Between Switches: 50 dB Typical at fis = 8 MHz, RL = 1 k Matched Control-Input to Signal-Output Capacitance: Reduces Output Signal Transients Frequency Response, Switch On = 40 MHz Typical 100% Tested for Quiescent Current at 20 V 5-V, 10-V, and 15-V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard No. 13-B, Standard Specifications for Description of B Series CMOS Devices Applications: Analog Signal Switching/Multiplexing: Signal Gating, Modulator, Squelch Control, Demodulator, Chopper, Commutating Switch Digital Signal Switching/Multiplexing Transmission-Gate Logic Implementation Analog-to-Digital and Digital-to-Analog Conversion Digital Control of Frequency, Impedance, Phase, and Analog-Signal Gain
Contact factory for details. Q100 qualification data available on request.
D OR PW PACKAGE (TOP VIEW)
SIG A IN/OUT SIG A OUT/IN SIG B OUT/IN SIG B IN/OUT CONTROL B CONTROL C VSS
VDD CONTROL A CONTROL D SIG D IN/OUT SIG D OUT/IN SIG C OUT/IN SIG C IN/OUT
description/ordering information
The CD4066B is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CD4016B, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full signal-input range.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated

POST OFFICE BOX 655303

DALLAS, TEXAS 75265
description/ordering information (continued)
The CD4066B consists of four bilateral switches, each with independent controls. Both the p and the n devices in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the n-channel device on each switch is tied to either the input (when the switch is on) or to VSS (when the switch is off). This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and, thus, keeps the on-state resistance low over the full operating-signal range. The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold applications, the CD4016B is recommended. ORDERING INFORMATION
TA 40C to 85C PACKAGE SOIC D TSSOP PW SOIC D TSSOP PW Reel of 2500 Reel of 2000 Reel of 2500 Reel of 2000 ORDERABLE PART NUMBER CD4066BIDRQ1 CD4066BIPWRQ1 CD4066BQDRQ1 CD4066BQPWRQ1 TOP-SIDE MARKING CD4066BI CM066BI CD4066BQ
CM066BQ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Product Preview Switch Control In Vis

40C to 125C

Out Vos

Control VC

VSS VDD
VSS All control inputs are protected by the CMOS protection network. NOTES: A. All p substrates are connected to VDD. B. Normal operation control-line biasing: switch on (logic 1), VC = VDD; switch off (logic 0), VC = VSS C. Signal-level range: VSS Vis VDD

92CS-29113

Figure 1. Schematic Diagram of One-of-Four Identical Switches and Associated Control Circuitry
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
DC supply-voltage range, VDD (voltages referenced to VSS terminal). 0.5 V to 20 V Input voltage range, Vis (all inputs). 0.5 V to VDD + 0.5 V DC input current, IIN (any one input). 10 mA Package thermal impedance, JA (see Note 1): D package. 112C/W PW package. 113C/W Lead temperature (during soldering): At distance 1/16 1/32 inch (1,59 0,79 mm) from case for 10 s max. 265C Storage temperature range, Tstg. 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions
MIN VDD TA Supply voltage I-suffix device Operating free-air temperature Q-suffix device 40 MAX 125 UNIT V C
electrical characteristics
LIMITS AT INDICATED TEMPERATURES PARAMETER TEST CONDITIONS VIN (V) 0, 5 IDD Quiescent device current 0, 10 0, 15 0, 20 Signal Inputs (Vis) and Outputs (Vos) VC = VDD, RL = 10 k returned V DD * V SS to , 2 Vis = VSS to VDD On-state resistance difference between any two switches Total harmonic distortion 3-dB cutoff frequency (switch on) 50-dB feedthrough frequency (switch off) Iis Input/output leakage current (switch off) (max) 50-dB crosstalk frequency Propagation delay (signal input to signal output) Input capacitance Output capacitance Feedthrough RL = 10 k, VC = VDD VC = VDD = 5 V, VSS = 5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 10 k, fis = 1-kHz sine wave VC = VDD = 5 V, VSS = 5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 1 k VC = VSS = 5 V, Vis(p-p) = 5 V (sine wave centered on 0 V), RL = 1 k VC = 0 V, Vis = 18 V, Vos = 0 V; and VC = 0 V, Vis = 0 V, Vos = 18 V VC(A) = VDD = 5 V, VC(B) = VSS = 5 V, Vis(A) = 5 Vp-p, 50- source, RL = 1 k RL = 200 k, VC = VDD, VSS = GND, CL = 50 pF, Vis = 10 V (square wave centered on 5 V), tr, tf = 20 ns VDD = 5 V, VC = VSS = 5 V VDD = 5 V, VC = VSS = 5 V VDD = 5 V, VC = VSS = 5 V 0.0.4 % 240 VDD (V) 25C 40C 0.25 0.5 85C 7.125C 7.TYP 0.01 0.01 0.01 0.02 MAX 0.25 0.5 A A UNIT
On-state resistance (max)

0.20 15

tpd Cis Cos Cios

ns pF pF pF

electrical characteristics (continued)
LIMITS AT INDICATED TEMPERATURES CHARACTERISTIC Control (VC) VILC Control input, low voltage (max) |Iis| < 10 A, Vis = VSS, VOS = VDD, and Vis = VDD, VOS = VSS VIHC Control input, high voltage Input current (max) Crosstalk (control input to signal output) Turn-on and turn-off propagation delay See Figure 6 Vis VDD, VDD VSS = 18 V, VCC VDD VSS VC = 10 V (square wave), tr, tf = 20 ns, RL = 10 k VIN = VDD, tr, tf = 20 ns, CL = 50 pF, RL = 1 k Vis = VDD, VSS = GND, RL = 1 k to GND, CL = 50 pF, k VC = 10 V (square wave centered on 5 V), tr, tf = 20 ns, Vos = 1/2 Vos at 1 kHz IIN 0.2 3.5 (MIN) 7 (MIN) 11 (MIN) 9.7.5 pF MHz 30 ns 0.1 A mV V 2 V TEST CONDITIONS VDD (V) 25C 40C 85C 125C TYP MAX UNIT

Maximum control input repetition rate CI Input capacitance
switching characteristics
SWITCH INPUT VDD (V) Vis (V) Iis (mA) 40C 0.61 0.61 1.5 1.4 25C 0.51 0.51 1.3 1.3 3.4 3.4 85C 0.42 0.42 1.1 1.1 2.8 2.8 125C 0.36 0.36 0.9 0.9 2.4 2.4 13.5 9.5 1.5 4.6 0.5 SWITCH OUTPUT, Vos (V) MIN MAX 0.4

TYPICAL CHARACTERISTICS

TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)
r Channel On-State Resistance on r Channel On-State Resistance on +25C 200 55C 4 Supply Voltage (VDD VSS) = 5 V TA = 125C 200 +25C 150 55C 7.2.2.7.5 10
Supply Voltage (VDD VSS) = 10 V TA = 125C
Vis Input Signal Voltage V

92CS-27326RI

92CS-27327RI

Figure 2

r Channel On-State Resistance on r Channel On-State Resistance on Supply Voltage (VDD VSS) = 15 V 200 TA = 125C 10 7.2.2.7.Vis Input Signal Voltage V

92CS-27329RI

Figure 3
TA = 125C V 10 7.2.2.7.15 V Supply Voltage (VDD VSS) = 5 V

+25C 55C

92CS-27330RI

Figure 4

Figure 5
Vis Iis CD4066B 1 of 4 Switches |Vis Vos| |Iis|

92CS-30966

Figure 6. Determination of ron as a Test Condition for Control-Input High-Voltage (VIHC) Specification
VDD TG On Keithley 160 Digital Multimeter 1-k Range
Y X-Y Plotter X H. P. Moseley 7030A

92CS-22716

Figure 7. Channel On-State Resistance Measurement Circuit
POWER DISSIPATION PER PACKAGE vs SWITCHING FREQUENCY
104 PD Power Dissipation Per Package W 3
TYPICAL ON CHARACTERISTICS FOR 1 OF 4 CHANNELS

TA = 25C

2 VO Output Voltage V
Supply Voltage (VDD) = 15 V 10 V 5V

CD4066B 14

VC = VDD

VDD Vos RL

CD4066B 1 of 4 Switches VSS
All unused terminals are connected to VSS

VI Input Voltage V

92CS-30919
f Switching Frequency kHz

Figure 8

Figure 9

92C-30920

VC = 5 V
VDD = 5 V VDD CD4066B 1 of 4 Switches VSS

92CS-30922

CD4066B 1 of 4 Switches Cis VSS = 5 V Cos

VC = VSS Vis = VDD

92CS-30921

Measured on Boonton capacitance bridge, model 75a (1 MHz); test-fixture capacitance nulled out.
All unused terminals are connected to VSS.
Figure 10. Typical On Characteristics for One of Four Channels
VC = VDD Vis VDD CD4066B 1 of 4 Switches VSS VDD tr = tf = 20 ns

92CS-30923

Figure 11. Off-Switch Input or Output Leakage
+10 V tr = tf = 20 ns 200 k
V Vis CD4066B os 1 of 4 Switches 10 k 1 k VSS

92CS-30924

Figure 12. Propagation Delay Time Signal Input (Vis) to Signal Output (Vos)
Figure 13. Crosstalk-Control Input to Signal Output
VDD tr = tf = 20 ns VC = VDD VDD
VDD CD4066B 1 of 4 Switches VSS 50 pF Vos
NOTES: A. All unused terminals are connected to VSS. B. Delay is measured at Vos level of +10% from ground (turn-on) or on-state output level (turn-off).

92CS-30925

Figure 14. Propagation Delay, tPLH, tPHL Control-Signal Output
tr VC 10% 90% 50% Repetition Rate tr = tf = 20 ns Vos

tf 10 V 0V

V OS +

V OS at 1 kHz 2

VDD = 10 V VC Vis = 10 V CD4066B 1 of 4 Switches VSS V OS + V OS at 1 kHz 2
Figure 15. Maximum Allowable Control-Input Repetition Rate

VDD Inputs

92CS-27555
Measure inputs sequentially to both VDD and VSS. Connect all unused inputs to either VDD or VSS. Measure control inputs only.
Figure 16. Input Leakage-Current Test Circuit
Clock Reset 1 Q1 QJJJJExternal Reset Clock 1 P E J1

P E J1

CD4018B

1/4 CD4066B

1/3 CD4049B Signal Inputs 2 1/6 CD4049B 10 k 12 CD4001B 7 1/3 CD4049B 10 6

CD4001B

2 Signal Outputs

Channel 1

Channel 1 Channel 2 Channel 3 Channel 4

CD4066B

Channel 2
Package Count 2 - CD4001B 1 - CD4049B 3 - CD4066B 2 - CD4018B

Channel 3

Maximum Allowable Signal Level
VDD 30% (VDD VSS) VSS Chan 1 Chan 2 Chan 3 Chan 4

LPF Channel 4

92CM-30928
Figure 17. Four-Channel PAM Multiplex System Diagram
5V V VDD = 5 V 5V 0 IN CD4054B CD4066B SWA SWB SWC SWD Digital Control Inputs VSS = 0 V VEE = 5 V VSS = 5 V

92CS-30927

Analog Inputs (5 V) VDD = 5 V

Analog Outputs (5 V)

Figure 18. Bidirectional Signal Transmission Via Digital Control Logic

APPLICATION INFORMATION

In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load of the four CD4066B bilateral switches). This provision avoids any permanent current flow or clamp action on the VDD supply when power is applied or removed from the CD4066B. In certain applications, the external load-resistor current can include both VDD and signal-line components. To avoid drawing VDD current when switch current flows into terminals 1, 4, 8, or 11, the voltage drop across the bidirectional switch must not exceed 0.8 V (calculated from ron values shown). No VDD current will flow through RL if the switch current flows into terminals 2, 3, 9, or 10.

PACKAGE OPTION ADDENDUM

www.ti.com

4-Apr-2011

PACKAGING INFORMATION
Orderable Device CD4066BQDRQ1 Status
Package Type Package Drawing SOIC D

Pins 14

Package Qty 2500

Eco Plan

Lead/ Ball Finish

MSL Peak Temp

Samples (Requires Login)

PREVIEW

Green (RoHS & no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD4066B-Q1 :
Catalog: CD4066B Military: CD4066B-MIL
NOTE: Qualified Version Definitions:

Addendum-Page 1

Catalog - TI's standard catalog product Military - QML certified for Military and Defense Applications

Addendum-Page 2

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