XCLKOUT

See GPIO18

XCLKIN

See GPIO19 and GPIO38
ADC, COMPARATOR, ANALOG I/O ADCINA7 ADCINA6 COMP3A AIO6 ADCINA5 ADCINA4 COMP2A AIO4 ADCINA3 ADCINA2 COMP1A AIO8 I I I I/O I I I I/O I I I I/O
TERMINAL NAME ADCINA1 PN PIN # 17 PAG PIN # 14 RSH PIN # 12 I/O/Z I ADC Group A, Channel 1 input ADC Group A, Channel 0 input. NOTE: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and their use is mutually exclusive to one another. NOTE: VREFHI and ADCINA0 share the same pin on the 56-pin RSH device and their use is mutually exclusive to one another. ADC External Reference only used when in ADC external reference mode. See Section 4.2.1, ADC. NOTE: VREFHI and ADCINA0 share the same pin on the 64-pin PAG device and their use is mutually exclusive to one another. NOTE: VREFHI and ADCINA0 share the same pin on the 56-pin RSH device and their use is mutually exclusive to one another. ADC Group B, Channel 7 input ADC Group B, Channel 6 input Comparator Input 3B Digital AIO 14 ADC Group B, Channel 5 input ADC Group B, Channel 4 input Comparator Input 2B Digital AIO12 ADC Group B, Channel 3 input ADC Group B, Channel 2 input Comparator Input 1B Digital AIO 10 ADC Group B, Channel 1 input ADC Group B, Channel 0 input NOTE: VREFLO is always connected to VSSA on the 64-pin PAG device and on the 56-pin RSH device. CPU AND I/O POWER VDDA VSSA VDD VDD VDD VDDIO VDDIO VSS VSS VSS VSS 51 Digital Ground Pins Analog Power Pin. Tie with a 2.2-F capacitor (typical) close to the pin. Analog Ground Pin. NOTE: VREFLO is always connected to VSSA on the 64-pin PAG device and on the 56-pin RSH device. CPU and Logic Digital Power Pins no supply source needed when using internal VREG. Tie with 1.2 F (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used, but could impact supply-rail ramp-up time. Digital I/O and Flash Power Pin Single Supply source when VREG is enabled DESCRIPTION

VREFHI

ADCINB7 ADCINB6 COMP3B AIO14 ADCINB5 ADCINB4 COMP2B AIO12 ADCINB3 ADCINB2 COMP1B AIO10 ADCINB1 ADCINB0 VREFLO

I I I I/O

TERMINAL NAME PN PIN # PAG PIN # RSH PIN # I/O/Z DESCRIPTION

Data Space 0x0x0x0x0x00 0D00

Prog Space

M0 Vector RAM (Enabled if VMAP = 0) M0 SARAM (1K x 16, 0-Wait) M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Reserved Peripheral Frame 0 CLA Registers CLA-to-CPU Message RAM CPU-to-CLA Message RAM Peripheral Frame 0 Reserved Peripheral Frame 1 (4K x 16, Protected)
0x00 0E00 0x0x0x0x0x0x00 6000
0xPeripheral Frame 2 (4K x 16, Protected) 0x0x0x00 8C00 0x0x00 A000 0x3D 7800 0x3D 7C00 0x3D 7C80 0x3D 7CC0 0x3D 7CE0 0x3D 7E80

Reserved

L0 SARAM (2K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) L1 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM 0) L2 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM 1) L3 DPSARAM (4K x 16) (0-Wait, Secure Zone + ECSL, CLA Prog RAM) Reserved User OTP (1K x 16, Secure Zone + ECSL) Reserved Calibration Data Get_mode function Reserved PARTID Calibration Data
0x3D 7EB0 Reserved 0x3E 8000 0x3F 7FF8 0x3F 8000 0x3F 8800 0x3F E000 0x3F FFC0 FLASH (64K x 16, 8 Sectors, Secure Zone + ECSL) 128-Bit Password L0 SARAM (2K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) Reserved Boot ROM (8K x 16, 0-Wait) Vector (32 Vectors, Enabled if VMAP = 1)
CLA-specific registers and RAM apply to the 28035 device only. Memory locations 0x3D7E80-0x3D7EAF are reserved in TMX silicon.
Figure 3-2. 28034/28035 Memory Map
0x3D 7EB0 Reserved 0x3F 0000 0x3F 7FF8 0x3F 8000 0x3F 8800 0x3F E000 0x3F FFC0 FLASH (32K x 16, 8 Sectors, Secure Zone + ECSL) 128-Bit Password L0 SARAM (2K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) Reserved Boot ROM (8K x 16, 0-Wait) Vector (32 Vectors, Enabled if VMAP = 1)
CLA-specific registers and RAM apply to the 28033 device only. Memory locations 0x3D7E80-0x3D7EAF are reserved in TMX silicon.
Figure 3-3. 28032/28033 Memory Map
M0 Vector RAM (Enabled if VMAP = 0) M0 SARAM (1K x 16, 0-Wait) M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Peripheral Frame 0 Reserved Peripheral Frame 1 (4K x 16, Protected)

0x00 0E00 0x0x00 6000

0xPeripheral Frame 2 (4K x 16, Protected) 0x0x0x00 8C00 0x0x0x3D 7800 0x3D 7C00 0x3D 7C80 0x3D 7CC0 0x3D 7CE0 0x3D 7E80
L0 SARAM (2K x 16) (0-Wait, Secure Zone + ECSL, Dual-Mapped) L1 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM 0) L2 DPSARAM (1K x 16) (0-Wait, Secure Zone + ECSL, CLA Data RAM 1) L3 DPSARAM (2K x 16) (0-Wait, Secure Zone + ECSL, CLA Prog RAM) Reserved User OTP (1K x 16, Secure Zone + ECSL) Reserved Calibration Data Get_mode function Reserved PARTID Calibration Data

3.3 3.3.1

Brief Descriptions CPU
The 2803x (C28x) family is a member of the TMS320C2000 microcontroller (MCU) platform. The C28x-based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very efficient C/C++ engine, enabling users to develop not only their system control software in a high-level language, but also enabling development of math algorithms using C/C++. The device is as efficient at MCU math tasks as it is at system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The device has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance.
Control Law Accelerator (CLA)
The C28x control law accelerator is a single-precision (32-bit) floating-point unit that extends the capabilities of the C28x CPU by adding parallel processing. The CLA is an independent processor with its own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks, or routines, can be specified. Each task is started by software or a peripheral such as the ADC, an ePWM, or CPU Timer 0. The CLA executes one task at a time to completion. When a task completes the main CPU is notified by an interrupt to the PIE and the CLA automatically begins the next highest-priority pending task. The CLA can directly access the ADC Result registers and the ePWM+HRPWM registers. Dedicated message RAMs provide a method to pass additional data between the main CPU and the CLA.
Memory Bus (Harvard Bus Architecture)
As with many MCU-type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows: Highest: Data Writes Program Writes Data Reads Program Reads Lowest: Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.) (Simultaneous program reads and fetches cannot occur on the memory bus.) (Simultaneous data and program writes cannot occur on the memory bus.) (Simultaneous data and program writes cannot occur on the memory bus.)

eCAN: LIN:

Register Map
The devices contain three peripheral register spaces. The spaces are categorized as follows: Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 3-8. Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See Table 3-9. Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table 3-10. Table 3-8. Peripheral Frame 0 Registers (1)
NAME ADDRESS RANGE 0x0x0x0x0x00 0A80 0x00 0ADF 0x00 0AE0 0x00 0AEF 0x00 0B00 0x00 0B0F 0x00 0C00 0x00 0C3F 0x00 0CE0 0x00 0CFF 0x00 0D00 0x00 0DFF 0x0x00 147F 0x0x00 14FF 0x0x00 157F SIZE (16) 128 EALLOW PROTECTED (2) Yes Yes Yes Yes No No No No Yes NA NA
Device Emulation Registers System Power Control Registers FLASH Registers (3) Code Security Module Registers ADC registers (0 wait read only) CPUTIMER0/1/2 Registers PIE Registers PIE Vector Table CLA Registers CLA to CPU Message RAM (CPU writes ignored) CPU to CLA Message RAM (CLA writes ignored) (1) (2) (3)
Registers in Frame 0 support 16-bit and 32-bit accesses. If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction disables writes to prevent stray code or pointers from corrupting register contents. The Flash Registers are also protected by the Code Security Module (CSM).
Table 3-9. Peripheral Frame 1 Registers
NAME eCAN-A registers Comparator 1 registers Comparator 2 registers ePWM1 + HRPWM1 registers ePWM2 + HRPWM2 registers ePWM3 + HRPWM3 registers ePWM4 + HRPWM4 registers ePWM5 + HRPWM5 registers ePWM6 + HRPWM6 registers ePWM7 + HRPWM7 registers eCAP1 registers eQEP1 registers LIN-A registers GPIO registers (1) ADDRESS RANGE 0x0x00 61FF 0x0x00 641F 0x0x00 643F 0x0x00 683F 0x0x00 687F 0x0x00 68BF 0x00 68C0 0x00 68FF 0x0x00 693F 0x0x00 697F 0x0x00 69BF 0x00 6A00 0x00 6A1F 0x00 6B00 0x00 6B3F 0x00 6C00 0x00 6C7F 0x00 6F80 0x00 6FFF SIZE (16) EALLOW PROTECTED
(1) (1) (1) (1) (1) (1) (1) (1) (1) (1)

(1) (1) (1)

Some registers are EALLOW protected. See the module reference guide for more information.
Table 3-10. Peripheral Frame 2 Registers
NAME System Control Registers SPI-A Registers SCI-A Registers NMI Watchdog Interrupt Registers External Interrupt Registers ADC Registers I2C-A Registers SPI-B Registers (1) ADDRESS RANGE 0x0x00 702F 0x0x00 704F 0x0x00 705F 0x0x00 706F 0x0x00 707F 0x0x00 717F 0x0x00 793F 0x0x00 774F SIZE (16) EALLOW PROTECTED Yes No No Yes Yes

(1) (1)

Device Emulation Registers

CLKCTL[INTOSC1OFF] 1 = Turn OSC Off
CLKCTL[INTOSC1HALT] 1 = Ignore HALT INTOSC2TRIM Reg
CLKCTL[OSCCLKSRCSEL] WAKEOSC Internal OSC2CLK OSC 2 (10 MHz) OSCE 0 OSCCLK (OSC1CLK on XRS reset) 1 CLKCTL[TRM2CLKPRESCALE] CLKCTL[TMR2CLKSRCSEL] PLL Missing-Clock-Detect Circuit
1 = Turn OSC Off CLKCTL[INTOSC2OFF]
Prescale /1, /2, /4, /8, /16 SYNC Edge Detect 00 OSCCLKSRC2 SYSCLKOUT
1 = Ignore HALT CLKCTL[INTOSC2HALT]

01, 10, 11 CPUTMR2CLK

XCLK[XCLKINSEL]

0 = GPIO= GPIO19

CLKCTL[OSCCLKSRC2SEL]
CLKCTL[XCLKINOFF] 0 XCLKIN GPIO19 or GPIO0 XCLKIN

X1 XTAL X2 (Crystal) OSC

EXTCLK WAKEOSC (Oscillators enabled when this signal is high)

CLKCTL[XTALOSCOFF]

0 = OSC on (default on reset) 1 = Turn OSC off
Register loaded from TI OTP-based calibration function. See Section 3.8.4 for details on missing clock detection.

Figure 3-10. Clock Tree

Internal Zero Pin Oscillators
The F2803x devices contain two independent internal zero pin oscillators. By default both oscillators are turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused oscillators may be powered down by the user. The center frequency of these oscillators is determined by their respective oscillator trim registers, written to in the calibration routine as part of the boot ROM execution. See Section 6, Electrical Specifications, for more information on these oscillators.
Crystal Oscillator Option
The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in Table 3-16. Furthermore, ESR range = 30 to 150. Table 3-16. Typical Specifications for External Quartz Crystal (1)
FREQUENCY (MHz) (1) Rd () CL1 (pF) CL2 (pF) 15 12
Cshunt should be less than or equal to 5 pF.

XCLKIN/GPIO19/38

Turn off XCLKIN path in CLKCTL register

Crystal

Figure 3-11. Using the On-chip Crystal Oscillator NOTE
1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the IC and crystal. The value is usually approximately twice the value of the crystal's load capacitance. 2. The load capacitance of the crystal is described in the crystal specifications of the manufacturers. 3. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range.
External Clock Signal (Toggling 0VDDIO)
Figure 3-12. Using a 3.3-V External Oscillator

PLL-Based Clock Module

The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) is at least 50 MHz. Table 3-17. PLL Settings

NMIFLG[NMINT] NMIFLGCLR[NMINT] Clear Latch Set Clear XRS
Generate Interrupt Pulse When Input = 1
NMIFLG[CLOCKFAIL] Clear Latch Clear Set NMIFLGCLR[CLOCKFAIL] CLOCKFAIL SYNC? SYSCLKOUT NMIFLGFRC[CLOCKFAIL]

NMICFG[CLOCKFAIL] XRS

SYSCLKOUT SYSRS NMIWDPRD[15:0] NMIWDCNT[15:0] NMI Watchdog NMIRS See System Control Section
Figure 3-13. NMI-watchdog

CPU-Watchdog Module

The CPU-watchdog module on the 2803x device is similar to the one used on the 281x/280x/283xx devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets the watchdog counter. Figure 3-14 shows the various functional blocks within the watchdog module. Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPU-watchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog counter stops decrementing (i.e., the watchdog counter does not change with the limp-mode clock). NOTE
The CPU-watchdog is different from the NMI watchdog. It is the legacy watchdog that is present in all 28x devices.
Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detecting failure of the flash memory.

WDCR (WDPS[2:0])

WDCR (WDDIS) WDCNTR(7:0)

WDCLK /512

Watchdog Prescaler
8-Bit Watchdog Counter CLR Clear Counter
Internal Pullup WDKEY(7:0) Watchdog 55 + AA Key Detector XRS Core-reset WDCR (WDCHK[2:0]) Bad WDCHK Key SCSR (WDENINT) WDRST Generate Output Pulse WDINT (512 OSCCLKs)

Good Key

WDRST(A)
The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-14. CPU-watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.9, Low-power Modes Block, for more details. In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode. In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset.

Comparator Block

Figure 4-5 shows the interaction of the Comparator modules with the rest of the system.
COMP x A COMP x B + COMP COMP x + DAC x Wrapper COMPxOUT DAC Core 10-Bit

TZ1/2/3

AIO MUX
Figure 4-5. Comparator Block Diagram Table 4-5. Comparator Control Registers
REGISTER NAME COMPCTL COMPSTS DACVAL COMP1 ADDRESS 0x6400 0x6402 0x6406 COMP2 ADDRESS 0x6420 0x6422 0x6426 COMP3 ADDRESS 0x6440 0x6442 0x6446 SIZE (x16) 1 EALLOW PROTECTED Yes No Yes DESCRIPTION Comparator Control Register Comparator Status Register DAC Value Register
Serial Peripheral Interface (SPI) Module
The device includes the four-pin serial peripheral interface (SPI) module. Up to two SPI modules are available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The SPI module features include: Four external pins: SPISOMI: SPI slave-output/master-input pin SPISIMO: SPI slave-input/master-output pin SPISTE: SPI slave transmit-enable pin SPICLK: SPI serial-clock pin NOTE: All four pins can be used as GPIO if the SPI module is not used. Two operational modes: master and slave Baud rate: 125 different programmable rates.
Baud rate = LSPCLK (SPIBRR + 1)

LSPCLK 4

when SPIBRR = 3 to 127

Baud rate =

when SPIBRR = 0, 1, 2
Data word length: one to sixteen data bits Four clocking schemes (controlled by clock polarity and clock phase bits) include: Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. Simultaneous receive and transmit operation (transmit function can be disabled in software) Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. Nine SPI module control registers: Located in control register frame beginning at address 7040h. NOTE

Figure 4-7. Serial Communications Interface (SCI) Module Block Diagram
Local Interconnect Network (LIN)
The device contains one LIN controller. The LIN standard is based on the SCI (UART) serial data link format. The LIN module can be configured to work as a SCI as well. The LIN module has the following features: Compatible to LIN 1.3 or 2.0 protocols Two external pins: LINRX and LINTX Multi-buffered receive and transmit units Identification masks for message filtering Automatic master header generation Programmable sync break field Sync field Identifier field Slave automatic synchronization Sync break detection Optional baudrate update Synchronization validation 231 programmable transmission rates with 7 fractional bits Wakeup on LINRX dominant level from transceiver Automatic wakeup support Wakeup signal generation Expiration times on wakeup signals Automatic bus idle detection Error detection Bit error Bus error No-response error Checksum error Sync field error Parity error 2 Interrupt lines with priority encoding for: Receive Transmit ID, error and status NOTE
The 2803x devices have passed LIN 2.0 conformance tests (master and slave). Contact TI for details.
The registers in Table 4-9 configure and control the operation of the LIN module. Table 4-9. LIN-A Registers (1)
NAME SCIGCR0 SCIGCR1 SCIGCR2 SCISETINT SCICLEARINT SCISETINTLVL SCICLEARINTLVL SCIFLR SCIINTVECT0 SCIINTVECT1 SCIFORMAT BRSR SCIED SCIRD SCITD Reserved SIPIO2 Reserved LINCOMP LINRD0 LINRD1 LINMASK LINID LINTD0 LINTD1 MBRSR Reserved IODFTCTRL (1) ADDRESS 0x6C00 0x6C02 0x6C04 0x6C06 0x6C08 0x6C0A 0x6C0C 0x6C0E 0x6C10 0x6C12 0x6C14 0x6C16 0x6C18 0x6C1A 0x6C1C 0x6C1E 0x6C22 0x6C24 0x6C30 0x6C32 0x6C34 0x6C36 0x6C38 0x6C3A 0x6C3C 0x6C3E 0x6C40 0x6C48 SIZE (x16) DESCRIPTION Global Control Register 0 Global Control Register 1 Global Control Register 2 Interrupt Enable Register Interrupt Disable Register Set Interrupt Level Register Clear Interrupt Level Register Flag Register Interrupt Vector Offset Register 0 Interrupt Vector Offset Register 1 Length Control register Baud Rate Selection Register Emulation buffer register Receiver data buffer register Transmit data buffer register RSVD Pin control register 2 RSVD Compare register Receive data register 0 Receive data register 1 Acceptance mask register Register containing ID- byte, ID-SlaveTask byte, and ID received fields. Transmit Data Register 0 Transmit Data Register 1 Baud Rate Selection Register RSVD IODFT for BLIN
Some registers and some bits in other registers are EALLOW-protected. See the TMS320x2803x Piccolo Local Interconnect Network (LIN) Module Reference Guide (literature number SPRUGE2) for more details.

EPWMSYNCI

EPWM1SYNCI EPWM1TZINT EPWM1INT EPWM2TZINT PIE EPWM2INT EPWMxTZINT EPWMxINT EPWM1 Module TZ4 TZ5 TZ6 TZ1 to TZ3 EQEP1ERR

EPWM1B

CLOCKFAIL EMUSTOP EPWM1ENCLK TBCLKSYNC eCAPI
EPWM1SYNCO EPWM1SYNCO COMPOUT1 COMPOUT2 EPWM2SYNCI EPWM2 Module TZ4 TZ5 TZ6 EQEP1ERR EMUSTOP EPWM2ENCLK TBCLKSYNC EPWM2SYNCO

TZ1 to TZ3 EPWM2B

EPWM1A H R P W M EPWM2A EPWMxA G P I O M U X EPWMxB

CLOCKFAIL

SOCA1 SOCB1 SOCA2 SOCB2 SOCAx SOCBx
EPWMxSYNCI EPWMx Module TZ4 TZ5 TZ6 TZ1 to TZ3 EQEP1ERR

EQEP1ERR

CLOCKFAIL EMUSTOP EPWMxENCLK TBCLKSYNC System Control C28x CPU eQEP1

SOCA1 SOCA2 SPCAx

Pulse Stretch (32 SYSCLKOUT Cycles, Active-Low Output)

ADCSOCAO

SOCB1 SOCB2 SPCBx

ADCSOCBO

This signal exists only on devices with an eQEP1 module.

Figure 4-12. ePWM

Table 4-13. ePWM1ePWM4 Control and Status Registers
NAME TBCTL TBSTS TBPHSHR TBPHS TBCTR TBPRD TBPRDHR CMPCTL CMPAHR CMPA CMPB AQCTLA AQCTLB AQSFRC AQCSFRC DBCTL DBRED DBFED TZSEL TZDCSEL TZCTL TZEINT TZFLG TZCLR TZFRC ETSEL ETPS ETFLG ETCLR ETFRC PCCTL HRCNFG (1) 78 ePWM1 0x6800 0x6801 0x6802 0x6803 0x6804 0x6805 0x6806 0x6807 0x6808 0x6809 0x680A 0x680B 0x680C 0x680D 0x680E 0x680F 0x6810 0x6811 0x6812 0x6813 0x6814 0x6815 0x6816 0x6817 0x6818 0x6819 0x681A 0x681B 0x681C 0x681D 0x681E 0x6820 ePWM2 0x6840 0x6841 0x6842 0x6843 0x6844 0x6845 0x6846 0x6847 0x6848 0x6849 0x684A 0x684B 0x684C 0x684D 0x684E 0x684F 0x6850 0x6851 0x6852 0x6853 0x6854 0x6855 0x6856 0x6857 0x6858 0x6859 0x685A 0x685B 0x685C 0x685D 0x685E 0x6860 ePWM3 0x6880 0x6881 0x6882 0x6883 0x6884 0x6885 0x6886 0x6887 0x6888 0x6889 0x688A 0x688B 0x688C 0x688D 0x688E 0x688F 0x6890 0x6891 0x6892 0x6893 0x6894 0x6895 0x6896 0x6897 0x6898 0x6899 0x689A 0x689B 0x689C 0x689D 0x689E 0x68A0 ePWM4 0x68C0 0x68C1 0x68C2 0x68C3 0x68C4 0x68C5 0x68C6 0x68C7 0x68C8 0x68C9 0x68CA 0x68CB 0x68CC 0x68CD 0x68CE 0x68CF 0x68D0 0x68D1 0x68D2 0x98D3 0x68D4 0x68D5 0x68D6 0x68D7 0x68D8 0x68D9 0x68DA 0x68DB 0x68DC 0x68DD 0x68DE 0x68E0 SIZE (x16) / #SHADOW 1/0 1/0 1/0 1/0 1/0 1/1 1/1 1/0 1/1 1/1 1/1 1/0 1/0 1/0 1/1 1/1 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 DESCRIPTION Time Base Control Register Time Base Status Register Time Base Phase HRPWM Register Time Base Phase Register Time Base Counter Register Time Base Period Register Set Time Base Period High Resolution Register (1) Counter Compare Control Register Time Base Compare A HRPWM Register Counter Compare A Register Set Counter Compare B Register Set Action Qualifier Control Register For Output A Action Qualifier Control Register For Output B Action Qualifier Software Force Register Action Qualifier Continuous S/W Force Register Set Dead-Band Generator Control Register Dead-Band Generator Rising Edge Delay Count Register Dead-Band Generator Falling Edge Delay Count Register Trip Zone Select Register (1) Trip Zone Digital Compare Register Trip Zone Control Register (1) Trip Zone Enable Interrupt Register (1) Trip Zone Flag Register

Trip Zone Clear Register (1) Trip Zone Force Register (1) Event Trigger Selection Register Event Trigger Prescale Register Event Trigger Flag Register Event Trigger Clear Register Event Trigger Force Register PWM Chopper Control Register HRPWM Configuration Register (1)
Registers that are EALLOW protected. Peripherals
Table 4-13. ePWM1ePWM4 Control and Status Registers (continued)
NAME HRPWR HRMSTEP HRPCTL TBPRDHRM TBPRDM CMPAHRM CMPAM DCTRIPSEL DCACTL DCBCTL DCFCTL DCCAPCT DCFOFFSET DCFOFFSETCNT DCFWINDOW DCFWINDOWCNT DCCAP (2) ePWM1 0x6821 0x6826 0x6828 0x682A 0x682B 0x682C 0x682D 0x6830 0x6831 0x6832 0x6833 0x6834 0x6835 0x6836 0x6837 0x6838 0x6839 ePWM2 0x6868 0x686A 0x686B 0x686C 0x686D 0x6870 0x6871 0x6872 0x6873 0x6874 0x6875 0x6876 0x6877 0x6878 0x6879 ePWM3 0x68A8 0x68AA 0x68AB 0x68AC 0x68AD 0x68B0 0x68B1 0x68B2 0x68B3 0x68B4 0x68B5 0x68B6 0x68B7 0x68B8 0x68B9 ePWM4 0x68E8 0x68EA 0x68EB 0x68EC 0x68ED 0x68F0 0x68F1 0x68F2 0x68F3 0x68F4 0x68F5 0x68F6 0x68F7 0x68F8 0x68F9 SIZE (x16) / #SHADOW 1/0 1/0 1/0 1/W 1/W
DESCRIPTION HRPWM Power Register HRPWM MEP Step Register High resolution Period Control Register (1) Time Base Period HRPWM Register Mirror Time Base Period Register Mirror Compare A HRPWM Register Mirror Compare A Register Mirror Digital Compare Trip Select Register

1 / W (2)

1 / W (2) 1/0 1/0 1/0 1/0 1/0 1/1 1/0 1/0 1/0 1/1
Digital Compare A Control Register (1) Digital Compare B Control Register (1) Digital Compare Filter Control Register (1) Digital Compare Capture Control Register (1) Digital Compare Filter Offset Register Digital Compare Filter Offset Counter Register Digital Compare Filter Window Register Digital Compare Filter Window Counter Register Digital Compare Counter Capture Register
W = Write to shadow register
Table 4-14. ePWM5ePWM7 Control and Status Registers
NAME TBCTL TBSTS TBPHSHR TBPHS TBCTR TBPRD TBPRDHR CMPCTL CMPAHR CMPA (1) ePWM5 0x6900 0x6901 0x6902 0x6903 0x6904 0x6905 0x6906 0x6907 0x6908 0x6909 ePWM6 0x6940 0x6941 0x6942 0x6943 0x6944 0x6945 0x6946 0x6947 0x6948 0x6949 ePWM7 0x6980 0x6981 0x6982 0x6983 0x6984 0x6985 0x6986 0x6987 0x6988 0x6989 SIZE (x16) / #SHADOW 1/0 1/0 1/0 1/0 1/0 1/1 1/1 1/0 1/1 1/1 Time Base Control Register Time Base Status Register Time Base Phase HRPWM Register Time Base Phase Register Time Base Counter Register Time Base Period Register Set Time Base Period High Resolution Register (1) Counter Compare Control Register Time Base Compare A HRPWM Register Counter Compare A Register Set DESCRIPTION

Zero-Pin Oscillator Frequency Movement With Temperature

10.6 10.5 10.4

Output Frequency (MHz)
10.3 10.2 10.9.9 9.8 9.7 9.6 40

Typical Max

Temperature (C)
Figure 6-6. Zero-Pin Oscillator Frequency Movement With Temperature
Clock Requirements and Characteristics
Table 6-6. XCLKIN Timing Requirements - PLL Enabled
NO. C9 C10 C11 C12 tf(CI) tr(CI) tw(CIL) tw(CIH) Fall time, XCLKIN Rise time, XCLKIN Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)

MAX 6 6

UNIT ns ns % %
Table 6-7. XCLKIN Timing Requirements - PLL Disabled
NO. C9 C10 C11 C12 tf(CI) tr(CI) tw(CIL) tw(CIH) Fall time, XCLKIN Rise time, XCLKIN Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) Up to 20 MHz 20 MHz to 30 MHz Up to 20 MHz 20 MHz to 30 MHz MIN MAX % % ns UNIT ns
The possible configuration modes are shown in Table 3-19. Table 6-8. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1)
NO. C3 C4 C5 C6 (1) (2) tf(XCO) tr(XCO) tw(XCOL) tw(XCOH) Fall time, XCLKOUT Rise time, XCLKOUT Pulse duration, XCLKOUT low Pulse duration, XCLKOUT high H2 H2 PARAMETER MIN TYP

MAX H+2 H+2

UNIT ns ns ns ns
A load of 40 pF is assumed for these parameters. H = 0.5tc(XCO)

C10 C8 XCLKIN(A) C9

XCLKOUT(B)
The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate the timing parameters only and may differ based on actual configuration. XCLKOUT configured to reflect SYSCLKOUT.

Figure 6-7. Clock Timing

Power Sequencing
There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up/down. However, it is recommended that no voltage larger than a diode drop (0.7 V) should be applied to any pin prior to powering up the device. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results.

VDDIO, VDDA (3.3 V)

VDD (1.8 V) INTOSC1 tINTOSCST X1/X2 tOSCST XCLKOUT (A) User-code dependent tw(RSL1) XRS
Address/data valid, internal boot-ROM code execution phase Address/Data/ Control (Internal)

td(EX) th(boot-mode)(C)

User-code execution phase User-code dependent

Boot-Mode Pins

GPIO pins as input Boot-ROM execution starts Peripheral/GPIO function Based on boot code

I/O Pins

GPIO pins as input (state depends on internal PU/PD) User-code dependent
Upon power up, SYSCLKOUT is OSCCLK/4. Since the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this phase. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that XCLKOUT will not be visible at the pin until explicitly configured by user code. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry.

t a(f p) - 1 round up to the next highest integer, or 1, whichever is larger Flash Page Wait State = t c(SCO) t a(f r) - 1 round up to the next highest integer, or 1, whichever is larger Flash Random Wait State = t c(SCO)
The equation to compute the OTP wait-state in Table 6-45 is as follows:
t a(OTP) - 1 round up to the next highest integer, or 1, whichever is larger OTP Wait State = t c(SCO)
7 D-to-E Revision History
This data sheet revision history highlights the technical changes made to the SPRS584D device-specific data sheet to make it an SPRS584E revision. Scope: Added 56-pin RSH package. NOTE: Information/data on the 56-pin RSH package is "TMX". The "TMX" product status denotes an experimental device that is not necessarily representative of the final device's electrical specifications. See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages. See table below.
LOCATION Global ADDITIONS, DELETIONS, AND MODIFICATIONS Added 56-pin RSH package. NOTE: Information/data on the 56-pin RSH package is "TMX". The "TMX" product status denotes an experimental device that is not necessarily representative of the final device's electrical specifications. See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages.
Section 1.1 Section 2.2 Table 2-2
Features: Removed "Community Resources" feature (see Section 5.3) Signal Descriptions: Added NOTE about using the on-chip VREG Terminal Functions: ADCINA5 (PN Pin# 13): Updated "I/O/Z" column and added DESCRIPTION VREFHI (PN Pin# 19, PAG Pin# 15, RSH Pin# 13): Updated "I/O/Z" column ADCINB5 (PN Pin# 28): Updated "I/O/Z" column and added DESCRIPTION ADCINB0 (PN Pin# 23, PAG Pin# 18): Added DESCRIPTION VREFLO (PN Pin# 22, PAG Pin# 17, RSH Pin# 15): Updated "I/O/Z" column LINTXA (PN Pin# 39, PAG Pin# 31): Updated "I/O/Z" column EPWM6B (PN Pin# 61, PAG Pin# 49): Updated "I/O/Z" column LINRXA (PN Pin# 61, PAG Pin# 49): Updated "I/O/Z" column Functional Block Diagram: Updated SARAM block Updated FLASH block 28034/28035 Memory Map: Removed Calibration Data block at 0x3D 7E80 Removed Reserved block at 0x3D 7EB0 Changed address of PARTID from "0x3D 7FFF" to "0x3D 7E80" Added Calibration Data block below PARTID block Changed address of Reserved block from "0x3D 8000" to "0x3D 7EB0" 28032/28033 Memory Map: Removed Calibration Data block at 0x3D 7E80 Removed Reserved block at 0x3D 7EB0 Changed address of PARTID from "0x3D 7FFF" to "0x3D 7E80" Added Calibration Data block below PARTID block Changed address of Reserved block from "0x3D 8000" to "0x3D 7EB0" 28031 Memory Map: Removed Calibration Data block at 0x3D 7E80 Removed Reserved block at 0x3D 7EB0 Changed address of PARTID from "0x3D 7FFF" to "0x3D 7E80" Added Calibration Data block below PARTID block Changed address of Reserved block from "0x3D 8000" to "0x3D 7EB0"

Section 2 Table 2-1

Section 2.1 Figure 2-2

Table 2-2

Section 3.3.19 Table 3-11 Table 3-16
C-to-D Revision History Submit Documentation Feedback focus.ti.com: TMS320F28030 TMS320F28031 TMS320F28032 TMS320F28033 TMS320F28034 TMS320F28035

LOCATION Section 4.2.1

ADDITIONS, DELETIONS, AND MODIFICATIONS ADC: Added Section 4.2.1.1, Features "ADC Connections if the ADC is Not Used" section: NOTE: Changed "They should be grounded through a resistor" to "They should be grounded through a 1-k resistor" Serial Peripheral Interface (SPI) Module: First paragraph: Changed "One SPI module (SPI-A) is available" to "Up to two SPI modules are available" Device Nomenclature: PACKAGE TYPE: Updated descriptions of 64-Pin PAG and 80-Pin PN Updated description of "Q" temperature range Electrical Characteristics: Removed "VDD BOR trip point" parameter Removed "VDD over-voltage trip point" parameter VREG VDD output: Removed MIN value of 1.865 V Removed MAX value of 1.955 V Updated footnote TMS320F2803x Current Consumption at 60-MHz SYSCLKOUT: VREG ENABLED: IDLE: Added IDDIO MAX of 23 mA STANDBY: Added IDDIO MAX of 9 mA Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics: Updated "In order to achieve better oscillator accuracy." footnote Added "Frequency range ensured only when VREG is enabled, VREGENZ = VSS" footnote IDLE Entry and Exit Timing: Added footnote about IDLE instruction and OSCCLK cycles STANDBY Entry and Exit Timing Diagram: Added footnote about IDLE instruction and OSCCLK cycles HALT Wake-Up Using GPIOn: Added footnote about IDLE instruction and OSCCLK cycles SPI Master Mode External Timing (Clock Phase = 0): Replaced drawing ADC Electrical Characteristics: Changed "VREFLO is always connected to VSSA" footnote to "VREFLO is always connected to VSSA on the 64-pin PAG device" Changed "VREFHI must not exceed VDDA when using either internal or external reference modes. Since VREFHI is tied to ADCINA0, the input signal on ADCINA0 must not exceed VDDA" footnote to "VREFHI must not exceed VDDA when using either internal or external reference modes. Since VREFHI is tied to ADCINA0 on the 64-pin PAG device, the input signal on ADCINA0 must not exceed VDDA" Changed title from "Flash Endurance for T Temperature Material" to "Flash/OTP Endurance for T Temperature Material" Flash/OTP Endurance for T Temperature Material: Added "ERASE/PROGRAM TEMPERATURE" column heading NOTP [OTP endurance for the array (write cycles)]: Changed temperature range from "0C to 105C (ambient)" to "0C to 30C (ambient)" Added "Flash/OTP Endurance for S Temperature Material" table Changed title from "Flash Endurance for Q and S Temperature Material" to "Flash/OTP Endurance for Q Temperature Material" Flash/OTP Endurance for Q Temperature Material: Added "ERASE/PROGRAM TEMPERATURE" column heading NOTP [OTP endurance for the array (write cycles)]: Changed temperature range from "40C to 125C (ambient)" to "40C to 30C (ambient)"