Texas Instruments TMS320F2812
TMS320F2812 eZdsp Start Kit (DSK); Development Tool Type:Hardware / Software - Starter Kit; Kit Contents:F2812 DSP, Code Composer Studio, power cord; MCU Supported Families:F2812
Brand: TEXAS INSTRUMENTS
Part Number: TMDSEZD2812
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User reviews and opinions
|helmutus||12:46am on Thursday, October 21st, 2010|
|Good Calculator I have found model calculator to be quite adequate for use in my undergraduate physics curriculum. In my opinion, it is optimal. According to my calculations... Awesome buy. Good condition, a little out of date, but still calculates numbers. No problems to report. Great product! This product is absolutely the best purchase I have made on Amazon. The sellers described it exactly as it was.|
|Ycaps123||4:29am on Saturday, October 16th, 2010|
|I wish that the USB cable were included instead of being an optional purchase. The teachers all require this calculator but truth be told. Everyone should own one of these for high school. Great calculator, easy to use. Manual is a little mass, but helpful. I was comparing this with ti-89.|
|grodger||4:03pm on Tuesday, August 10th, 2010|
|Graphing. This is a work-of-art! It was recommended in a maths book - well worth the money: there is so much that you can do with it! Review Just to add to the previous review, its also great fun for playing games on!!! ;-)|
|rsahgal||12:52am on Sunday, August 8th, 2010|
|Its required to have one at my school during our senior year. Adequate Capabilities, Clear Display, Easy To Use, Long Battery Life Bulky|
|Dmiry||4:23pm on Wednesday, July 21st, 2010|
|This is a great calculator. It takes a little while to learn all of its feature, but that is only because it has so many. I love this calculator. Best graphing calculator available|
|quangtrung||2:01am on Saturday, July 3rd, 2010|
|it is very well made to work with algebra and calculus. it does not break easily when dropped. the graphing on the calculator is superb and unmatched. The TI 83 Plus is an excellent calculator for use in high school. From making graphs, to finding functions and variable equations.|
|stefan_lb||3:15pm on Saturday, April 10th, 2010|
|I use it a lot when I went to 1st year algebra. I find it very useful in many cases. It helped me a lot in homework and tests. Therefore. it gets me where i need to go! Adequate Capabilities, Attractive Design, Clear Display, Long Battery Life Bulky|
|dbwisc||3:45pm on Friday, March 19th, 2010|
|Disappointed This calculator arrived without the instruction manual or cable as was advertised. Additionally there was no packaging therefore.|
Comments posted on www.ps2netdrivers.net are solely the views and opinions of the people posting them and do not necessarily reflect the views or opinions of us.
IDLE Mode Switching Characteristics STANDBY Mode Timing Requirements
6-61 6-62 6-63 6-64 6-65 6-66 8-1 8-2 8-3 8-4
Flash Endurance for Q Temperature Material... 156 Flash Parameters at 150-MHz SYSCLKOUT... 156 Flash/OTP Access Timing.... 157 Minimum Required Flash Wait States at Different Frequencies (F281x devices).. 157 ROM Access Timing... 158 Minimum Required ROM Wait States at Different Frequencies (C281x devices).. 158 Thermal Resistance Characteristics for 179-Ball GHH... 161 Thermal Resistance Characteristics for 179-Ball ZHH... 161 Thermal Resistance Characteristics for 176-Pin PGF... 161 Thermal Resistance Characteristics for 128-Pin PBK
Check for Samples: TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812
TMS320F281x, TMS320C281x DSPs
Clock and System Control Dynamic PLL Ratio Changes Supported On-Chip Oscillator Watchdog Timer Module Three External Interrupts Peripheral Interrupt Expansion (PIE) Block That Supports 45 Peripheral Interrupts Three 32-Bit CPU-Timers 128-Bit Security Key/Lock Protects Flash/ROM/OTP and L0/L1 SARAM Prevents Firmware Reverse-Engineering Motor Control Peripherals Two Event Managers (EVA, EVB) Compatible to 240xA Devices Serial Port Peripherals Serial Peripheral Interface (SPI) Two Serial Communications Interfaces (SCIs), Standard UART Enhanced Controller Area Network (eCAN) Multichannel Buffered Serial Port (McBSP) 12-Bit ADC, 16 Channels 2 x 8 Channel Input Multiplexer Two Sample-and-Hold Single/Simultaneous Conversions Fast Conversion Rate: 80 ns/12.5 MSPS Up to 56 General-Purpose I/O (GPIO) Pins Advanced Emulation Features Analysis and Breakpoint Functions Real-Time Debug via Hardware Development Tools Include ANSI C/C++ Compiler/Assembler/Linker Code Composer Studio IDE DSP/BIOS JTAG Scan Controllers(1) Low-Power Modes and Power Savings IDLE, STANDBY, HALT Modes Supported Disable Individual Peripheral Clocks
High-Performance Static CMOS Technology 150 MHz (6.67-ns Cycle Time) Low-Power (1.8-V Core @135 MHz, 1.9-V Core @150 MHz, 3.3-V I/O) Design JTAG Boundary Scan Support (1) High-Performance 32-Bit CPU ( TMS320C28x) 16 x 16 and 32 x 32 MAC Operations 16 x 16 Dual MAC Harvard Bus Architecture Atomic Operations Fast Interrupt Response and Processing Unified Memory Programming Model 4M Linear Program/Data Address Reach Code-Efficient (in C/C++ and Assembly) TMS320F24x/LF240x Processor Source Code Compatible On-Chip Memory Flash Devices: Up to 128K x 16 Flash (Four 8K x 16 and Six 16K x 16 Sectors) ROM Devices: Up to 128K x 16 ROM 1K x 16 OTP ROM L0 and L1: 2 Blocks of 4K x 16 Each Single-Access RAM (SARAM) H0: 1 Block of 8K x 16 SARAM M0 and M1: 2 Blocks of 1K x 16 Each SARAM Boot ROM (4K x 16) With Software Boot Modes Standard Math Tables External Interface (2812) Over 1M x 16 Total Memory Programmable Wait States Programmable Read/Write Strobe Timing Three Individual Chip Selects
PIN NO. NAME 179-BALL GHH/ZHH 176-PIN PGF 128-PIN PBK I/O/Z (2) PU/PD (3) DESCRIPTION
JTAG AND MISCELLANEOUS SIGNALS Oscillator Input input to the internal oscillator. This pin is also used to feed an external clock. The 28x can be operated with an external clock source, provided that the proper voltage levels be driven on the X1/XCLKIN pin. It should be noted that the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core digital power supply (VDD), rather than the 3.3-V I/O supply (VDDIO). A clamping diode may be used to clamp a buffered clock signal to ensure that the logic-high level does not exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator may be used. Oscillator Output Output clock derived from SYSCLKOUT to be used for external wait-state generation and as a general-purpose clock source. XCLKOUT is either the same frequency, 1/2 the frequency, or 1/4 the frequency of SYSCLKOUT. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting bit 3 (CLKOFF) of the XINTCNF2 register to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in a high-impedance state during reset. Test Pin. Reserved for TI. Must be connected to ground. Device Reset (in) and Watchdog Reset (out). Device reset. XRS causes the device to terminate execution. The PC will point to the address contained at the location 0x3FFFC0. When XRS is brought to a high level, execution begins at the location pointed to by the PC. This pin is driven low by the DSP when a watchdog reset occurs. During watchdog reset, the XRS pin will be driven low for the watchdog reset duration of 512 XCLKIN cycles. The output buffer of this pin is an open-drain with an internal pullup (100 A, typical). It is recommended that this pin be driven by an open-drain device. Test Pin. Reserved for TI. On F281x devices, TEST1 must be left unconnected. On C281x devices, this pin is a no connect (NC) (i.e., this pin is not connected to any circuitry internal to the device). Test Pin. Reserved for TI. On F281x devices, TEST2 must be left unconnected. On C281x devices, this pin is a no connect (NC) (i.e., this pin is not connected to any circuitry internal to the device).
External Interface (XINTF) (2812 Only)
This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for extending wait states externally or not. The programmable wait-state, chip-select and programmable strobe timing enables glueless interface to external memories and peripherals.
Flash (F281x Only)
The F2812 and F2811 contain 128K x 16 of embedded flash memory, segregated into four 8K x 16 sectors, and six 16K x 16 sectors. The F2810 has 64K x 16 of embedded flash, segregated into two 8K x 16 sectors, and three 16K x 16 sectors. All three devices also contain a single 1K x 16 of OTP memory at address range 0x3D 78000x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information. NOTE
The F2810/F2811/F2812 Flash and OTP wait states can be configured by the application. This allows applications running at slower frequencies to configure the flash to use fewer wait states. Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent. For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the TMS320x281x DSP System Control and Interrupts Reference Guide (literature number SPRU078).
ROM (C281x Only)
The C2812 and C2811 contain 128K x 16 of ROM. The C2810 has 64K x 16 of ROM. In addition to this, there is a 1K x 16 ROM block that replaces the OTP memory available in flash devices. For information on how to submit ROM codes to TI, see the TMS320C28x CPU and Instruction Set Reference Guide (literature number SPRU430).
3.2.18 Peripheral Frames 0, 1, 2 (PFn)
The F281x and C281x segregate peripherals into three sections. The mapping of peripherals is as follows: PF0: XINTF: PIE: Flash: Timers: CSM: PF1: PF2: eCAN: SYS: GPIO: EV: McBSP: SCI: SPI: ADC: External Interface Configuration Registers (2812 only) PIE Interrupt Enable and Control Registers Plus PIE Vector Table Flash Control, Programming, Erase, Verify Registers CPU-Timers 0, 1, 2 Registers Code Security Module KEY Registers eCAN Mailbox and Control Registers System Control Registers GPIO Mux Configuration and Control Registers Event Manager (EVA/EVB) Control Registers McBSP Control and TX/RX Registers Serial Communications Interface (SCI) Control and RX/TX Registers Serial Peripheral Interface (SPI) Control and RX/TX Registers 12-Bit ADC Registers
3.2.19 General-Purpose Input/Output (GPIO) Multiplexer
Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This multiplexing enables use of a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured as inputs. The user can then individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles to filter unwanted noise glitches.
3.2.20 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for the DSP/BIOS Real-Time OS, and is connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.
3.2.21 Control Peripherals
The F281x and C281x support the following peripherals that are used for embedded control and communication: EV: The event manager module includes general-purpose timers, full-compare/PWM units, capture inputs (CAP) and quadrature-encoder pulse (QEP) circuits. Two such event managers are provided which enable two three-phase motors to be driven or four two-phase motors. The event managers on the F281x and C281x are compatible to the event managers on the 240x devices (with some minor enhancements). The ADC block is a 12-bit converter, single ended, 16-channels. It contains two sample-and-hold units for simultaneous sampling.
1.8 V can use the same 1.8-V (or 1.9-V) supply as the digital core but separate the two with a ferrite bead or a filter Digital Ground
Provide access to this pin in PCB layouts. Intended for test purposes only. Use 24.9 k for ADC clock range 118.75 MHz; use 20 k for ADC clock range 18.7525 MHz. TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, or equivalent ceramic capacitor External decoupling capacitors are recommended on all power pins. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance.
Figure 4-5. ADC Pin Connections With Internal Reference NOTE
The temperature rating of any recommended component must match the rating of the end product.
ADC 16-Channel Analog Inputs Test Pin ADC External Current Bias Resistor ADC Reference Positive Input ADC Reference Medium Input
ADCINA[7:0] ADCINB[7:0] ADCLO ADCBGREFIN ADCRESEXT ADCREFP ADCREFM
Analog Input 0-3 V With Respect to ADCLO Connect to Analog Ground 24.9 k /20 k
2V 1V 1 F - 10 F 1 F - 10 F
VDDA1 VDDA2 VSSA1 VSSA2 AVDDREFBG AVSSREFBG VDDAIO VSSAIO VDD1 VSS1
Analog 3.3 V Analog 3.3 V
ADC Reference Power
Analog 3.3 V
ADC Analog I/O Power
Analog 3.3 V Analog Ground
A. B. C. D.
1.8 V can use the same 1.8-V (or 1.9-V) Digital Ground supply as the digital core but separate the two with a ferrite bead or a filter External decoupling capacitors are recommended on all power pins. Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance. Use 24.9 k for ADC clock range 118.75 MHz; use 20 k for ADC clock range 18.7525 MHz. It is recommended that buffered external references be provided with a voltage difference of (ADCREFP ADCREFM) = 1 V 0.1% or better. External reference is enabled using bit 8 in the ADCTRL3 Register at ADC power up. In this mode, the accuracy of external reference is critical for overall gain. The voltage ADCREFP ADCREFM will determine the overall accuracy. Do not enable internal references when external references are connected to ADCREFP and ADCREFM. See the TMS320x281x DSP Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) for more information. ADC Digital Power
Figure 4-6. ADC Pin Connections With External Reference
The ADC operation is configured, controlled, and monitored by the registers listed in Table 4-4. Table 4-4. ADC Registers (1)
LSPCLK (SPIBRR + 1)
when SPIBRR 0
when SPIBRR = 0, 1, 2, 3
Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted such that the peripheral speed is less than the I/O buffer speed limit20 MHz maximum. Data word length: one to sixteen data bits Four clocking schemes (controlled by clock polarity and clock phase bits) include: Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. Simultaneous receive and transmit operation (transmit function can be disabled in software) Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. Nine SPI module control registers: Located in control register frame beginning at address 7040h. NOTE: All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (70), and the upper byte (158) is read as zeros. Writing to the upper byte has no effect.
Enhanced features: 16-level transmit/receive FIFO Delayed transmit control
The SPI port operation is configured and controlled by the registers listed in Table 4-10. Table 4-10. SPI Registers (1)
NAME SPICCR SPICTL SPISTS SPIBRR SPIRXEMU SPIRXBUF SPITXBUF SPIDAT SPIFFTX SPIFFRX SPIFFCT SPIPRI (1) ADDRESS 0x0x0x0x0x0x0x0x0x00 704A 0x00 704B 0x00 704C 0x00 704F SIZE (x16) SPI Operation Control Register SPI Status Register SPI Baud Rate Register SPI Receive Emulation Buffer Register SPI Serial Input Buffer Register SPI Serial Output Buffer Register SPI Serial Data Register SPI FIFO Transmit Register SPI FIFO Receive Register SPI FIFO Control Register SPI Priority Control Register DESCRIPTION SPI Configuration Control Register
These registers are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
Figure 4-11 is a block diagram of the SPI in slave mode.
SPIFFENA SPIFFTX.14 RX FIFO Registers SPIRXBUF RX FIFO _0 RX FIFO _1 ----RX FIFO _SPIRXBUF Buffer Register TX FIFO Interrupt SPI INT FLAG SPISTS.6 SPICTL.0 SPIFFOVF FLAG SPIFFRX.15 TX FIFO Registers SPITXBUF TX FIFO _15 ----TX FIFO _1 TX FIFO _SPITXBUF Buffer Register 16 TX Interrupt Logic SPI INT ENA Receiver Overrun Flag SPISTS.7 SPICTL.4 RX FIFO Interrupt Overrun INT ENA
Total 3.3-V current
Test conditions are as defined in Table 6-1 for operational currents. IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn by VDD1. IDDA represents the current drawn by VDDA1 and VDDA2 rails. Total 3.3-V current is the sum of IDDIO, IDD3VFL, and IDDA. It includes a small amount of current (<1 mA) drawn by VDDAIO.
Figure 6-1. F2812/F2811/F2810 Typical Current Consumption Over Frequency
Figure 6-2. F2812/F2811/F2810 Typical Power Consumption Over Frequency
Test conditions are as defined in Table 6-2 for operational currents. IDD represents the total current drawn from the 1.8-V rail (VDD). It includes a small amount of current (<1 mA) drawn by VDD1. IDDA represents the current drawn by VDDA1 and VDDA2 rails. Total 3.3-V current is the sum of IDDIO and IDDA. It includes a small amount of current (<1 mA) drawn by VDDAIO.
Figure 6-3. C2812/C2811/C2810 Typical Current Consumption Over Frequency
Figure 6-4. C2812/C2811/C2810 Typical Power Consumption Over Frequency
Reducing Current Consumption
28x DSPs incorporate a unique method to reduce the device current consumption. A reduction in current consumption can be achieved by turning off the clock to any peripheral module which is not used in a given application. Table 6-3 indicates the typical reduction in current consumption achieved by turning off the clocks to various peripherals. Table 6-3. Typical Current Consumption by Various Peripherals (at 150 MHz) (1)
PERIPHERAL MODULE eCAN EVA EVB ADC SCI SPI McBSP (1) (2) IDD CURRENT REDUCTION (mA) (2) 13
All peripheral clocks are disabled upon reset. Writing to/reading from peripheral registers is possible only after the peripheral clocks are turned on. This number represents the current drawn by the digital portion of the ADC module. Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (IDDA) as well.
Emulator Connection Without Signal Buffering for the DSP
Figure 6-5 shows the connection between the DSP and JTAG header for a single-processor configuration. If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-5 shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.
6 inches or less VDDIO VDDIO
EMU0 EMU1 TRST TMS TDI TDO TCK DSP
EMU0 EMU1 TRST TMS TDI TDO TCK TCK_RET JTAG Header
GND GND GND GND GND
Figure 6-5. Emulator Connection Without Signal Buffering for the DSP
Power Sequencing Requirements
TMS320F2812/F2811/F2810 silicon requires dual voltages (1.8-V or 1.9-V and 3.3-V) to power up the CPU, Flash, ROM, ADC, and the I/Os. To ensure the correct reset state for all modules during power up, there are some requirements to be met while powering up/powering down the device. The current F2812 silicon reference schematics (Spectrum Digital Incorporated eZdsp board) suggests two options for the power sequencing circuit. Power sequencing is not needed for C281x devices. In other words, 3.3-V and 1.8-V (or 1.9-V) can ramp together. C281x can also be used on boards that have F281x power sequencing implemented; however, if the 1.8-V (or 1.9-V) rail lags the 3.3-V rail, the GPIO pins are undefined until the 1.8-V rail reaches at least 1 V. Option 1: In this approach, an external power sequencing circuit enables VDDIO first, then VDD and VDD1 (1.8 V or 1.9 V). After 1.8 V (or 1.9 V) ramps, the 3.3 V for Flash (VDD3VFL) and ADC (VDDA1/VDDA2/AVDDREFBG) modules are ramped up. While option 1 is still valid, TI has simplified the requirement. Option 2 is the recommended approach. Option 2: Enable power to all 3.3-V supply pins (VDDIO, VDD3VFL, VDDA1/VDDA2/VDDAIO/AVDDREFBG) and then ramp 1.8 V (or 1.9 V) (VDD/VDD1) supply pins. 1.8 V or 1.9 V (VDD/VDD1) should not reach 0.3 V until VDDIO has reached 2.5 V. This ensures the reset signal from the I/O pin has propagated through the I/O buffer to provide power-on reset to all the modules inside the device. See Figure 6-11 for power-on reset timing. Power-Down Sequencing: During power-down, the device reset should be asserted low (8 s, minimum) before the VDD supply reaches 1.5 V. This will help to keep on-chip flash logic in reset prior to the VDDIO/VDD power supplies ramping down. It is recommended that the device reset control from Low-Dropout (LDO) regulators or voltage supervisors be used to meet this constraint. LDO regulators that facilitate power-sequencing (with the aid of additional external components) may be used to meet the power sequencing requirement. See www.spectrumdigital.com for F2812 eZdsp schematics and updates. Table 6-4. Recommended Low-Dropout Regulators
SUPPLIER Texas Instruments PART NUMBER TPS767D301
The GPIO pins are undefined until VDD = 1 V and VDDIO = 2.5 V.
(E) 3.3 V 3.3 V
<10 ms 1.8 V (or 1.9 V) VDD_1.8V
1.8 V (or 1.9 V)
>8 s XRS
A. B. C. D. E. F. G. H.
VDD_3.3V VDDIO, VDD3VFL, VDDAIO, VDDA1, VDDA2, AVDDREFBG VDD_1.8V VDD, VDD1 1.8-V (or 1.9-V) supply should ramp after the 3.3-V supply reaches at least 2.5 V. Reset (XRS) should remain low until supplies and clocks are stable. See Figure 6-11, Power-on Reset in Microcomputer Mode (XMP/MC = 0), for minimum requirements. Voltage supervisor or LDO reset control will trip reset (XRS) first when the 3.3-V supply is off regulation. Typically, this occurs a few milliseconds before the 1.8-V (or 1.9-V) supply reaches 1.5 V. Keeping reset low (XRS) at least 8 s prior to the 1.8-V (or 1.9-V) supply reaching 1.5 V will keep the flash module in complete reset before the supplies ramp down. Since the state of GPIO pins is undefined until the 1.8-V (or 1.9-V) supply reaches at least 1 V, this supply should be ramped as quickly as possible (after the 3.3-V supply reaches at least 2.5 V). Other than the power supply pins, no pin should be driven before the 3.3-V rail has been fully powered up.
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 6-9. 3.3-V Test Load Circuit
6.13 Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options available on the F281x and C281x DSPs. Table 6-5 lists the cycle times of various clocks. Table 6-5. TMS320F281x and TMS320C281x Clock Table and Nomenclature
MIN On chip oscillator clock XCLKIN SYSCLKOUT XCLKOUT HSPCLK LSPCLK ADC clock SPI clock McBSP XTIMCLK (1) (2) tc(OSC), Cycle time Frequency tc(CI), Cycle time Frequency tc(SCO), Cycle time Frequency tc(XCO), Cycle time Frequency tc(HCO), Cycle time Frequency tc(LCO), Cycle time Frequency tc(ADCCLK), Cycle time (2) Frequency tc(SPC), Cycle time Frequency tc(CKG), Cycle time Frequency tc(XTIM), Cycle time Frequency 6.13.3 188.8.131.52.67 0.5 6.67 13.3 (1) 75
MAX 150 75
UNIT ns MHz ns MHz ns MHz ns MHz ns MHz ns MHz ns MHz ns MHz ns MHz ns MHz
26.6 (1) 37.5 (1)
This is the default reset value if SYSCLKOUT = 150 MHz. The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.
6.14 Clock Requirements and Characteristics 6.14.1 Input Clock Requirements
The clock provided at the XCLKIN pin generates the internal CPU clock cycle. Table 6-6. Input Clock Frequency
PARAMETER Resonator fx Input clock frequency Crystal XCLKIN fl Limp mode clock frequency Without PLL With PLL MIN 2 TYP MAX MHz MHz UNIT
Table 6-7. XCLKIN Timing Requirements PLL Bypassed or Enabled
NO. C8 C9 C10 C11 C12 tc(CI) tf(CI) tr(CI) tw(CIL) tw(CIH) Cycle time, XCLKIN Fall time, XCLKIN Rise time, XCLKIN Pulse duration, X1/XCLKIN low as a percentage of tc(CI) Pulse duration, X1/XCLKIN high as a percentage of tc(CI) MIN 6.67 MAX 60 UNIT ns ns ns % %
Figure 6-16. STANDBY Entry and Exit Timing
Table 6-16. HALT Mode Timing Requirements
MIN tw(WAKE-XNMI) tw(WAKE-XRS) Pulse duration, XNMI wakeup signal Pulse duration, XRS wakeup signal 2tc(CI) 8tc(CI) NOM MAX UNIT cycles cycles
Table 6-17. HALT Mode Switching Characteristics
PARAMETER td(IDLE-XCOH) tp Delay time, IDLE instruction executed to XCLKOUT high PLL lock-up time Delay time, PLL lock to program execution resume td(WAKE) Wake up from flash Flash module in sleep state Wake up from SARAM 1125tc(SCO) 35tc(SCO) cycles cycles MIN 32tc(SCO) TYP 45tc(SCO) 131072tc(CI) MAX UNIT cycles cycles
A B Device Status Flushing Pipeline
C D HALT HALT PLL Lock-up Time Wake-up Latency
XNMI tw(WAKE-XNMI) tp td(wake)
X1/XCLKIN td(IDLE-XCOH) XCLKOUT
Oscillator Start-up Time
32 SYSCLKOUT Cycles
E. F. G. H.
IDLE instruction is executed to put the device into HALT mode. The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush properly. Clocks to the peripherals are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode and consumes absolute minimum power. When XNMI is driven active, the oscillator is turned on; but the PLL is not activated. The pulse duration of 2tc(CI) is applicable when an external oscillator is used. If the internal oscillator is used, the oscillator wake-up time should be added to this parameter. When XNMI is deactivated, it initiates the PLL lock sequence, which takes 131,072 X1/XCLKIN cycles. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited. Normal operation resumes. XCLKOUT = SYSCLKOUT
Figure 6-17. HALT Wakeup Using XNMI
6.17 Event Manager Interface 6.17.1 PWM Timing
PWM refers to all PWM outputs on EVA and EVB. Table 6-18. PWM Switching Characteristics (1) (2)
PARAMETER tw(PWM) (3) td(PWM)XCO (1) (2) (3) Pulse duration, PWMx output high/low Delay time, XCLKOUT high to PWMx output switching XCLKOUT = SYSCLKOUT/4 TEST CONDITIONS MIN MAX UNIT ns ns
See the GPIO output timing for fall/rise times for PWM pins. PWM pin toggling frequency is limited by the GPIO output buffer switching frequency (20 MHz). PWM outputs may be 100%, 0%, or increments of tc(HCO) with respect to the PWM period.
6.30.2 ADC Electrical Characteristics Over Recommended Operating Conditions
Table 6-44. DC Specifications (1)
PARAMETER Resolution ADC clock (2) ACCURACY INL (Integral nonlinearity) Offset error (4) Overall gain error with internal reference (5) Overall gain error with external reference (6) Channel-to-channel offset variation Channel-to-channel Gain variation ANALOG INPUT Analog input voltage (ADCINx to ADCLO) (7) ADCLO Input capacitance Input leakage current INTERNAL VOLTAGE REFERENCE (5) Accuracy, ADCVREFP Accuracy, ADCVREFM Voltage difference, ADCREFP ADCREFM Temperature coefficient Reference noise EXTERNAL VOLTAGE REFERENCE (6) Accuracy, ADCVREFP Accuracy, ADCVREFM Input voltage difference, ADCREFP ADCREFM (1) (2) (3) (4) (5) 1.9 0.95 0.2.1 1.05 1.01 V V V 1.9 0.2.1 1.05 V V V PPM/C V V mV pF A F281x C281x If ADCREFP ADCREFM = 1 V 0.1%
MIN 12 1
UNIT Bits kHz
25 118.75 MHz ADC clock 118.75 MHz ADC clock 1.80 50
MHz LSB LSB LSB LSB LSB LSB LSB
DNL (Differential nonlinearity) (3)
Tested at 12.5-MHz ADCCLK. If SYSCLKOUT 25 MHz, ADC clock SYSCLKOUT/2. The INL degrades for frequencies beyond 18.75 MHz25 MHz. Applications that require these sampling rates should use a 20K resistor as bias resistor on the ADCRESEXT pin. This improves overall linearity and typical current drawn by the ADC will be a few mA more than 24.9-k bias. The ADC module in C281x devices can operate at 24.9k bias on ADCRESEXT pin for the full range 125 MHz. 1 LSB has the weighted value of 3.0/4096 = 0.732 mV. A single internal band gap reference (5% accuracy) sources both ADCREFP and ADCREFM signals, and hence, these voltages track together. The ADC converter uses the difference between these two as its reference. The total gain error will be the combination of the gain error shown here and the voltage reference accuracy (ADCREFP ADCREFM). A software-based calibration procedure is recommended for better accuracy. See the F2810, F2811, and F2812 ADC Calibration Application Report (literature number SPRA989) and Section 5.2, Documentation Support, for relevant documents. In this mode, the accuracy of external reference is critical for overall gain. The voltage difference (ADCREFP ADCREFM) will determine the overall accuracy. Voltages above VDDA + 0.3 V or below VSS 0.3 V applied to an analog input pin may temporarily affect the conversion of another pin. To avoid this, the analog inputs should be kept within these limits.
Table 6-45. AC Specifications
PARAMETER SINAD SNR THD (100 kHz) ENOB (SNR) SFDR Signal-to-noise ratio + distortion Signal-to-noise ratio Total harmonic distortion Effective number of bits Spurious free dynamic range MIN TYP 68 10.MAX UNIT dB dB dB Bits dB
6.30.6 Sequential Sampling Mode (Single-Channel) (SMODE = 0)
In sequential sampling mode, the ADC can continuously convert input signals on any of the channels (Ax to Bx). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software trigger, or from an external ADCSOC signal. If the SMODE bit is 0, the ADC will do conversions on the selected channel on every Sample/Hold pulse. The conversion time and latency of the Result register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The selected channels will be sampled at every falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum).
Sample n+2 Sample n+1 Analog Input on Channel Ax or Bx Sample n
ADC Clock Sample and Hold SH Pulse SMODE Bit td(SH) tdschx_n ADC Event Trigger from EV or Other Sources tSH tdschx_n+1
Figure 6-41. Sequential Sampling Mode (Single-Channel) Timing Table 6-48. Sequential Sampling Mode Timing
SAMPLE n td(SH) tSH Delay time from event trigger to sampling Sample/ Hold width/ Acquisition width Delay time for first result to appear in the Result register Delay time for successive results to appear in the Result register 2.5tc(ADCCLK) (1 + Acqps) * tc(ADCCLK) 40 ns with Acqps = 0 Acqps value = 015 ADCTRL1[8:11] SAMPLE n + 1 AT 25-MHz ADC CLOCK, tc(ADCCLK) = 40 ns REMARKS
(2 + Acqps) * tc(ADCCLK)
6.30.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels (A0/B0 to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB), software trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected channels on every Sample/Hold pulse. The conversion time and latency of the Result register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update. The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC clocks wide (maximum). NOTE
In Simultaneous Mode, the ADCIN channel pair select has to be A0/B0, A1/B1,., A7/B7, and not in other combinations (such as A1/B3, etc.).
Sample n Analog Input on Channel Ax Analog Input on Channel Bv ADC Clock Sample and Hold SH Pulse SMODE Bit ADC Event Trigger from EV or Other Sources tSH Sample n+1
SYSCLKOUT (MHz) 4 (1) SYSCLKOUT (ns) 6.67 184.108.40.206.PAGE WAIT STATE (1) 0 RANDOM WAIT STATE (1) 1
Formulas to compute page wait state and random wait state:
t a(fp) - 1 (round up to the next highest integer, or 0, whichever is larger) Flash Page Wait State = t c(SCO) t a(fr) - 1 (round up to the next highest integer, or 1, whichever is larger) Flash Random Wait State = t c(SCO) t a(OTP) - 1 (round up to the next highest integer, or 1, whichever is larger) OTP Wait State = t c(SCO)
(2) Random wait state must be greater than or equal to 1.
6.33 ROM Timing (C281x only)
Table 6-65. ROM Access Timing
PARAMETER ta(rp) ta(rr) ta(ROM) (1) Paged ROM access time Random ROM access time ROM (OTP area) access time (1) MIN 60 MAX UNIT ns ns ns
In C281x devices, a 1K 16 ROM block replaces the OTP block found in Flash devices.
Table 6-66. Minimum Required ROM Wait States at Different Frequencies (C281x devices)
t a(rp) - 1 (round up to the next highest integer, or 0, whichever is larger) ROM Page Wait State = t c(SCO) t a(rr) - 1 (round up to the next highest integer, or 1, whichever is larger) ROM Random Wait State = t c(SCO)
6.34 Migrating From F281x Devices to C281x Devices
The migration issues to be considered while migrating from the F281x devices to C281x devices are as follows: The 1K OTP memory available in F281x devices has been replaced by 1K ROM in C281x devices. Power sequencing is not needed for C281x devices. In other words, 3.3-V and 1.8-V (or 1.9-V) can ramp together. C281x can also be used on boards that have F281x power sequencing implemented; however, if the 1.8-V (or 1.9-V) rail lags the 3.3-V rail, the GPIO pins are undefined until the 1.8-V rail reaches at least 1 V. Current consumption differs for F281x and C281x devices for all four possible modes. See the appropriate electrical section for exact numbers. The VDD3VFL pin is the 3.3-V flash core power pin in F281x devices but is a VDDIO pin in C281x devices. F281x and C281x devices are pin-compatible and code-compatible; however, they are electrically different with different EMI/ESD profiles. Before ramping production with C281x devices, evaluate performance of the hardware design with both devices. Addresses 0x3D 7BFC through 0x3D 7BFF in the OTP and addresses 0x3F 7FF2 through 0x3F 7FF5 in the main ROM array are reserved for ROM part-specific information and are not available for user applications. The ADC module in C281x devices can operate at 24.9k bias on ADCRESEXT pin for the full range 125 MHz. While migrating the F281x designs to C281x, use a 24.9k resistor for biasing the ADC. The paged and random wait-state specifications for the flash and ROM parts are different. While migrating from flash to ROM parts, the same wait-state values must be used for best performance compatibility (for example, in applications that use software delay loops or where precise interrupt latencies are critical). The PART-ID register value is different for Flash and ROM parts. For errata applicable to 281x devices, see the TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, TMS320C2812 DSP Silicon Errata (literature number SPRZ193).
R E A L
W O R L D
S I G N A L
P R O C E S S I N G
Industrys most powerful 32-bit, 150-MIPS DSP core with single-cycle 32 32-bit MAC Highest integration with one quarter Megabyte fast-access Flash memory and 12-bit Analog-toDigital Converter (ADC) Most C/C++ efficient DSP with 1.1 C-to-Assembly ratio and virtual floating-point programming
TMS320F2810 and TMS320F2812 32-Bit Fixed-Point Flash DSPs
The new DSPs from Texas Instruments give designers of embedded applications a powerful way to dramatically increase system performance while reducing design complexity. The highly integrated 32-bit Flash-based F2810 and F2812 DSPs are revolutionary in many ways: The 32-bit TMS320C28x DSP core is the industrys most powerful fixed-point architecture capable of 150 MIPS of performance and a single-cycle 32 32-bit MAC. These new devices combine together with the C28x DSP core, a large amount of fastaccess Flash memory, highprecision analog peripherals, and many other control and communication modules making these devices the industrys most integrated DSPs. The C28x DSP core is the most C/C++ efficient of the industry with a C-to-Assembly ratio of 1.1 and a unique virtual floating-point programming capability.
The Foundation for Success The C28x DSP Core
The F2810 and F2812 DSPs are the first catalog devices based on TIs code-compatible C28x 32-bit DSP core. Optimized for embedded applications, the C28x DSP core features an innovative unified architecture that combines the best of generalpurpose processors and DSPs. The core features a roadmap to
400 MIPS of computational bandwidth to handle in real-time numerous sophisticated algorithms, including: Precision PID and multivariable control Adaptive control and parameter estimation Spectrum analysis Compression/Decompression Communication protocols and software embedded modems
TMS320C2000 DSP Roadmap
The TMS320C2000 DSP platform roadmap offers a broad range of solutions from sub-$2.00 to 150 MIPS.
In addition to higher performance and integration, the C28x DSP core also features the industrys highest code-efficiency and full code compatibility with every device in the TMS320C2000 platform. Software code compatibility enables designers to take code already developed for current TMS320C24x DSPs and port it directly to the F2810 or F2812 DSPs. Compatibility also allows manufacturers to quickly develop product variations by taking the code and matching it with a processor optimized for a particular application.
TMS320F2812 DSP Block Diagram
The F2810 and F2812 DSPs
The F2810 and F2812 DSPs feature 150-MIPS performance and complete system-on-a-chip integration that greatly reduces board space and system cost, leading to simpler and more costeffective designs. The F2812 DSP integrates 128 Kw of Flash memory while the F2810 DSP features 64 Kw of Flash for easy reprogramming in development and in-field software updates. TIs Flash acceleration technology allows code execution out of Flash at 110 to 120 MIPS, while time-critical code that requires higher performance can be executed at 150 MIPS directly through on-chip RAM. The F2810 DSP is packaged in a 128pin low-profile quad flat pack (LQFP), and the F2812 DSP is available in a 179-pin MicroStar BGA or 176-pin LQFP.
The F2812 DSP provides the industrys highest level of Flash and peripheral integration.
tions constant focus on reducing design complexity and cost, while increasing performance for embedded applications. Control peripherals include: A 12-bit, 16-channel ADC capable of producing a 200-ns single conversion; or, in the case of multiple sampling, 60 ns per conversion. Optimized event managers, including flexible PWM generators, programmable generalpurpose timers and glueless capture encoder interfaces. The devices also feature several standard communication ports for easy connection to other system components such as CPUs, serial EEPROMs, LCD displays and external data converters. In addition, a Controller Area Network (CAN) peripheral provides a glueless connection to CAN networks for a variety of applications, including industrial, automotive and telecom backplane.
Fast Development Time With Ultra-Efficient Compiler
TI designed the 32-bit C28x DSP hardware and compiler software to work hand-in-hand for maximum code efficiency and ease of use. The F2810 and F2812 DSPs allow developers to write both system and math code completely in C/C++, dramatically reducing development time and freeing designers to focus on value-added differentiating
Integrated, lower-cost designs with on-chip peripherals
By integrating control peripherals and communications ports, the F2810 and F2812 DSPs contribute to the C28x DSP genera-
features. In addition, all C28x DSPs feature 32-bit math capabilities and a unique IQ math library that allows designers to port floating-point algorithms to a fixed-point machine in minutes, producing the look and feel of a floating-point machine on a cost-effective, fixed-point architecture.
TMS320F2810/F2812 DSP Features
Feature Instruction cycle (at 150 MHz) Single-access RAM (SARAM) (16-bit word) On-chip Flash (16-bit word) Code security for on-chip Flash/SARAM Boot ROM (16-bit word) OTP ROM (16-bit word) External Memory Interface Event Managers General-purpose (GP) timers Compare (CMP)/PWM Capture (CAP)/QEP channels 12-bit, 16-channel ADC, 16.7 MSPS Watchdog timer 32-bit CPU timers SPI SCI (UART) CAN McBSP Digital I/O pins (shared) External interrupts Supply voltage Packaging Product status F2810 DSP 6.67 ns 18K 64K Yes 4K 2K No 16 6/2 Yes Yes 3 Yes 2 Yes Yes F2812 DSP 6.67 ns 18K 128K Yes 4K 2K Yes 16 6/2 Yes Yes 3 Yes 2 Yes Yes 56 3
Start Development Today
Designers can get started today with support from TIs Code Composer Studio Development Tools. The highly integrated, intuitive platform supports the F2810 and F2812 DSPs with eXpressDSP Software and Development Tools, featuring DSP/BIOS real-time kernel. DSP/BIOS provides a complete set of instrumented kernel services optimized for fast execution speed. It also features a priority-based scheduler along with a set of real-time analysis tools and an RTDX data link between host computer and target DSP.
1.8-V core, 3.3-V I/O 1.8-V core, 3.3-V I/O 179-pin *BGA 128-pin LQFP 176-pin LQFP Available Available
Also available to designers, the TMS320F2812 eZdsp DSP Starter Kit (DSK) is a low-cost, self-contained, stand-alone
TMS320F2812 eZdsp DSP Starter Kit
development platform for the F2810 and F2812 DSPs. It enables developers to simplify code development and reduce debugging time and is fully compatible with the Code Composer Studio development suite. This software tool chain provides the user with a C compiler, assembler, linker and Windowsbased debugger.
For More Information
To learn more about the F2810 and F2812 DSPs, which are available today, contact your field sales representative or review complete technical documentation at: www.dspvillage.ti.com/c28xbulletin
The F2812 DSK offers a complete set of development tools to aid the developer in digital control.
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