4 QUICK REFERENCE DATA SYMBOL VDD VDDA IDD(pd) PARAMETER supply voltage supply voltage for step-up converter supply current in Power-down mode VDD = 3.3 V; cards inactive; XTAL oscillator stopped VDD = 3.3 V; cards active at VCC = 5 V; CLK stopped; XTAL oscillator stopped IDD(sm) IDD(oper) supply current in sleep mode supply current in operating mode cards powered at 5 V; clock stopped VDD = 3.3 V; fXTAL = 20 MHz; VCC1 = VCC2 = 5 V; ICC1 + ICC2 = 80 mA 5 V card including static loads with 40 nC dynamic loads on 200 nF capacitor 3 V card including static loads with 24 nC dynamic loads on 200 nF capacitor 1.8 V card including static loads with 12 nC dynamic loads on 200 nF capacitor ICC card supply output current 5 V card; operating 3 V card; operating 1.8 V card; operating overload detection ICC1 + ICC2 sum of both card supply output currents SR tdeact tact fXTAL fext Tamb slew rate on VCC (rise and fall) deactivation cycle duration activation cycle duration crystal frequency external frequency ambient temperature applied to pin XTAL1 operating; 5 and 3 V cards CL(max) = 300 nF 1.65 1.62 0.05 40 100 0.16 2.78 2.75 4.75 4.6 5.0 CONDITIONS MIN. 2.7 VDD

TYP.

MAX. 350 3

UNIT V V A mA

5.5 315
card supply output voltage

5.25 5.4

3.22 3.25

1.95 1.80 0.20 +85

V V mA mA mA mA mA V/s s s MHz MHz C
5 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8007BHL/C2 TDA8007BHL/CLQFP48 LQFP48 DESCRIPTION
VERSION SOT313-2 SOT313-2
plastic low prole quad at package; 48 leads; body 1.4 mm plastic low prole quad at package; 48 leads; body 1.4 mm

BLOCK DIAGRAM

handbook, full pagewidth

100 nF GND 19

220 nF
220 nF SBP SBM AGND VUP 220 nF

RSTOUT DELAY nF

SAP SAM 26

SUPPLY AND SUPERVISOR

STEP-UP CONVERTER
INT ALE AD0 AD1 AD2 AD3 RD WR D0 D1 D2 D3 D4 D5 D6 D7 CS I/OAUX INTAUX
ISO7816 UART INTERFACE CONTROL ANALOG DRIVERS AND SEQUENCERS TIME-OUT COUNTER 17 CLOCK CIRCUIT 15
C41 C81 CLK1 RST1 VCC1 I/O1 PRES1 CGND1 C42 C82 CLK2 RST2 VCC2 I/O2 PRES2 CGND2

INT OSC

XTAL OSC 47 XTALXTAL2

FCE534

Fig.1 Block diagram.
7 PINNING SYMBOL RSTOUT I/OAUX I/O1 C81 PRES1 C41 CGND1 CLK1 VCC1 RST1 I/O2 C82 PRES2 C42 CGND2 CLK2 VCC2 RST2 GND VUP SAP SBP VDDA SBM AGND SAM VDD D0 D1 D2 D3 D4 D5 D6 DFeb 18 PIN 35 DESCRIPTION PMOS open-drain output for resetting external devices input or output for an I/O line from an auxiliary smart card interface input or output for the data line to/from card 1 (ISO C7 contact) auxiliary I/O for ISO C8 contact (synchronous cards, for instance) for card 1 card 1 presence contact input (active HIGH) auxiliary I/O for ISO C4 contact (synchronous cards, for instance) for card 1 ground for card 1; must be connected to GND clock output to card 1 (ISO C3 contact) card 1 supply output voltage (ISO C1 contact) card 1 reset output (ISO C2 contact) input or output for the data line to/from card 2 (ISO C7 contact) auxiliary I/O for ISO C8 contact (synchronous cards, for instance) for card 2 card 2 presence contact input (active HIGH) auxiliary I/O for ISO C4 contact (synchronous cards, for instance) for card 2 ground for card 2; must be connected to GND clock output to card 2 (ISO C3 contact) card 2 supply output voltage (ISO C1 contact) card 2 reset output (ISO C2 contact) ground

connection for the step-up converter capacitor; connect a low ESR capacitor of 220 nF to AGND contact 1 for the step-up converter; connect a low ESR capacitor of 220 nF between pins SAP and SAM contact 3 for the step-up converter; connect a low ESR capacitor of 220 nF between pins SBP and SBM positive analog supply voltage for the step-up converter; may be higher than VDD; decouple with a good quality capacitor to GND contact 4 for the step-up converter; connect a low ESR capacitor of 220 nF between pins SBP and SBM analog ground for the step-up converter contact 2 for the step-up converter; connect a low ESR capacitor of 220 nF between pins SAP and SAM positive supply voltage; decouple with a good quality capacitor to GND input/output of data 0 or address 0 input/output of data 1 or address 1 input/output of data 2 or address 2 input/output of data 3 or address 3 input/output of data 4 or address 4 input/output of data 5 or address 5 input/output of data 6 or address 6 input/output of data 7 or address 7 6
SYMBOL RD WR CS ALE INT INTAUX AD3 AD2 AD1 AD0 XTAL2 XTAL1 DELAY

PIN 48

DESCRIPTION read selection input; read or write in non-multiplexed conguration (active LOW) write selection input; enable in case of non-multiplexed conguration (active LOW) chip select input (active LOW) address latch enable input in case of multiplexed conguration; connect to VDD in non-multiplexed conguration NMOS interrupt output (active LOW) auxiliary interrupt input register selection address 3 input register selection address 2 input register selection address 1 input register selection address 0 input connection for an external crystal connection for an external crystal or input for an external clock signal connection for an external delay capacitor

41 INTAUX

48 DELAY

47 XTAL1

46 XTAL2

45 AD0

44 AD1

43 AD2

42 AD3

39 ALE

RSTOUT I/OAUX I/O1 C81 PRES1 C41 CGND1 CLK1 VCC1

40 INT

36 RD 35 DDDDD3

TDA8007BHL

DDDVDD 26 SAM 25 AGND

RSTI/OC82 12

PRES2 13

C42 14

CGND2 15

CLK2 16

VCC2 17

RST2 18

GND 19

VUP 20

SAP 21

SBP 22

VDDA 23

SBM 24

FCE678

Fig.2 Pin configuration.

8 FUNCTIONAL DESCRIPTION
read, a LOW pulse on pin WR allows the selected register to be written to. Using a 80C51 microcontroller, the TDA8007BHL/C is simply controlled with MOVX instructions. 8.1.2 NON-MULTIPLEXED CONFIGURATION
Throughout this specification, it is assumed that the reader is aware of ISO 7816 norm terminology. 8.1 Interface control
The TDA8007BHL/C can be controlled via an 8-bit parallel bus (bits D0 to D7). 8.1.1 MULTIPLEXED CONFIGURATION
If a microcontroller with a multiplexed address and data bus (such as the 80C51) is used, then pins D0 to D7 may be directly connected to ports P0 to P7. Automatic switching to the multiplexed bus configuration (see Fig.3) occurs: In TDA8007BHL/C2; if a rising edge is detected on signal ALE and CS is LOW In TDA8007BHL/C3; if a rising edge is detected on signal ALE. In this event, pins AD0 to AD3 play no role and may be tied to VDD or ground. When signal CS = LOW (see Fig.4), the demultiplexing of address and data is performed internally using signal ALE, a LOW pulse on pin RD allows the selected register to be
If pin ALE is tied to VDD or ground, the TDA8007BHL/C will be in the non-multiplexed configuration. In this case, the address bits are determined by means of pins AD0 to AD3; the read or write control signal is on pin RD and a data write or read active LOW enable signal is on pin WR. In non-multiplexed bus configuration, signals CS and WR play the same role. In read operations (see Fig.5) with signal RD = HIGH, the data corresponding to the chosen address is available on the bus when both signals CS and WR are LOW. In write operations (see Figs.6 and 7) with signal RD = LOW, the data present on the bus is written when signals CS and WR are LOW. In both configurations, the TDA8007BHL/C is selected only when signal CS = LOW. Signal INT is an active LOW interrupt signal.
AD0 to AD3 CS D0 to D7 ALE WR RD LATCH REC MUX MUX addresses RD WR REGISTERS

FCE679

Fig.3 Multiplexed bus recognition.
handbook, full pagewidth ALE

tW(ALE) CS

tW(RD)
tAVLL t(RWH-AH) t(AL-RWL)

t(RWH-AH)

t(AL-RWL) D0 to D7 ADDRESS DATA READ ADDRESS t(DV-WL) RD t(RL-DV) WR

FCE680

DATA WRITE

tW(WR)

Fig.4 Control with multiplexed bus (read and write).

AD0 to AD3

RD t1 CS t2 t3

D0 to D7

DATA OUT

FCE840

Fig.5 Control with non-multiplexed bus (read).
RD t7 CS t6 WR t4 D0 to D7 DATA IN

FCE841

Fig.6 Control with non-multiplexed bus (write release with signal CS).

RD t7 CS

WR t6 D0 to D7 t4 DATA IN

FCE842

Fig.7 Control with non-multiplexed bus (write release with signal EN).

8.2 Control registers

In reception mode, a FIFO of 1 to 8 characters may be used and is configured with the FIFO Control Register (FCR). This register is also used for the automatic re-transmission of Not AcKnowledged (NAK) characters in transmission mode. The Hardware Status Register (HSR) gives the status of the supply voltage, of the hardware protections and of the card movements. Registers HSR and USR give interrupts on pin INT when some of their bits have been changed. Register MSR does not give interrupts and may be used in the polling mode for some operations; for this use, some of the interrupt sources within the registers USR and HSR may be masked. A 24-bit time-out counter may be started to give an interrupt after a number of ETU programmed into the Time-Out Registers TOR1, TOR2 and TOR3. This will help the microcontroller in processing different real-time tasks (ATR, WWT, BWT, etc.). This counter is configured with a Time-Out counter Configuration (TOC) register. It may be used as a 24-bit counter or as a 16-bit plus 8-bit counter. Each counter can be set to start counting once data has been written, or on detection of a START bit on the I/O, or as auto-reload.
The TDA8007BHL/C has two complete analog interfaces which can drive cards 1 and 2. The data to and from these two cards shares the same ISO UART. The data to and from a third card (card 3), externally interfaced (with a TDA8020 or TDA8004 for example), may also share the same ISO UART. Cards 1, 2 and 3 have dedicated registers for setting the parameters of the ISO UART (see Fig.8): Programmable Divider Register (PDR) Guard Time Register (GTR) UART Configuration Register 1 (UCR1) UART Configuration Register 2 (UCR2) Clock Configuration Register (CCR). Cards 1 and 2 also have dedicated registers for controlling their power and clock configuration. The Power Control Register (PCR) for card 3 is controlled externally. Register PCR is also used for writing or reading on the auxiliary card contacts C4 and C8. Card 1, 2 or 3 can be selected via the Card Select Register (CSR). When one card is selected, the corresponding parameters are used by the ISO UART. Register CSR also contains one bit for resetting the ISO UART (bit RIU = 0). This bit is reset after power-on and must be set to logic 1 before starting with any one of the cards. It may be reset by software when necessary. When the specific parameters of the cards have been programmed, the UART may be used with the following registers: UART Receive Register (URR) UART Transmit Register (UTR) UART Status Register (USR) Mixed Status Register (MSR).

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GENERAL

CARD SELECT REGISTER HARD STATUS REGISTER TIME-OUT REGISTER 1

ISO UART

UART STATUS REGISTER UART TRANSMIT REGISTER

TIME-OUT REGISTER 2

MIXED STATUS REGISTER

UART RECEIVE REGISTER

TIME-OUT REGISTER 3

FIFO CONTROL REGISTER

TIME-OUT CONFIGURATION

CARD 1

CARD 2
PROGRAM DIVIDER REGISTER 2

CARD 3

PROGRAM DIVIDER REGISTER 3
Fig.8 Summary of registers.
PROGRAM DIVIDER REGISTER 1

GUARD TIME REGISTER 1

GUARD TIME REGISTER 2

GUARD TIME REGISTER 3

UART CONFIGURATION REGISTER 11
UART CONFIGURATION REGISTER 21
UART CONFIGURATION REGISTER 31
UART CONFIGURATION REGISTER 12
UART CONFIGURATION REGISTER 22
UART CONFIGURATION REGISTER 32
CLOCK CONFIGURATION REGISTER 1
CLOCK CONFIGURATION REGISTER 2
CLOCK CONFIGURATION REGISTER 3

FCE682

POWER CONTROL REGISTER 1

POWER CONTROL REGISTER 2

8.2.1 GENERAL REGISTERS

8.2.1.1

Card select register
The Card Select Register (CSR) is used for selecting the card on which the UART will act, and also to reset the ISO UART. Table CS7 Note 1. Register value at reset: all significant bits are cleared after reset, except bits CS7 to CS4 which are set to their default value. Table 2 BIT 3 Description of CSR bits; note 1 SYMBOL CS7 CS6 CS5 CS4 RIU Reset ISO UART. When reset, this bit resets a large part of the UART registers to their initial value. Bit RIU must be reset before any activation; logic 0 for at least 10 ns duration. Bit RIU must be set to logic 1 by software before any action on the UART can take place. Select Card 3. If bit SC3 = 1, then card 3 is selected. Select Card 2. If bit SC2 = 1, then card 2 is selected. Select Card 1. If bit SC1 = 1, then card 1 is selected. DESCRIPTION IC identication. Default value for identifying the IC: 0010 = TDA8007BHL/C= TDA8007BHL/C3 Register CSR (address 00H; write and read); note CSCSCSRIU 2 SCSCSC1

Synchronous/asynchronous card. Bit SAN = 1 by software if a synchronous card is expected. The UART is then bypassed and only bit 0 in registers URR and UTR is connected to pin I/O. In this case the clock is controlled by bit SC in register CCR. Auto convention. If bit AUTOCONV = 1, then the convention is set by software using bit CONV in register UCR1. If the bit is reset, then the configuration is automatically detected on the first received character whilst the start session (bit SS) is set. Bit AUTOCONV must not be changed during a card session.

AUTOCONV

Clock UART. For baud rates other than those given in Table 21, there is the possibility to set bit CKU = 1. In this case, the ETU will last half the number of card clock cycles equal to prescaler PDRx. Note that bit CKU = 1 has no effect if fCLK = fXTAL. This means, for example, that 76800 baud is not possible when the card is clocked with the external frequency on pin XTAL1. PreScale Select. If bit PSC = 1, then the prescaler value is 32. If bit PSC = 0, then the prescaler value is 31. One ETU will last a number of cards clock cycles equal to prescaler PDRx. All baud rates specified in the ISO 7816 norm are achievable with this configuration (see Table 21).
Table 21 Baud rate selection using values F and D; card clock frequency fCLK = 3.58 MHz for PSC = 31 and fCLK = 4.92 MHz for PSC = 32 (example; in the table 31;12 means prescaler set to 31 and PDR set to 12) F D 9 31;1 31;115200 31;31;31;31;31;32;31;31;31;1 31;31;31;2 31;31;3 31;31;31;31;4 31;31;31;5 31;31;31;31;31;6 31;31;31;9 32;32;32;32;32;10 32;32;32;32;11 32;32;32;32;32;32;32;12 32;32;32;32;32;13 32;32;32;32;32;32;2 76800

8.2.3.3

Guard time register
The Guard Time Registers (GTR1, GTR2 and GTR3) are used for storing the number of guard ETU given by the card during ATR. In transmission mode, the UART will wait this number of ETU before transmitting the character stored in register UTR. When register GTRx = FF: In protocol T = 1 TDA8007BHL/C2 operates at 11 ETU TDA8007BHL/C3 operates at 10.8 ETU In protocol T = 0 TDA8007BHL/C2 operates at 12 ETU TDA8007BHL/C3 operates at 11.8 ETU. Table 22 Registers GTR1, GTR2 and GTR3 (address 05H; read and write); note GT7 Note 1. Register value at reset: all bits are cleared after reset. 6 GTGTGTGTGTGTGT0

8.2.3.4 UART conguration register 1
The UART Configuration Registers 1 (UCR11, UCR21 and UCR31) set the parameters of the ISO UART. Table 23 Registers UCR11, UCR21 and UCR31 (address 06H; read and write); note UC17 Note 1. Register value at reset: all relevant bits are cleared after reset. Table 24 Description of UCR1 bits BIT 3 SYMBOL UC17 FIP FC PROT T/R not used Force Inverse Parity. If bit FIP is set to logic 1, the UART will NAK a correctly received character, and will transmit characters with wrong parity bits. Test. Bit FC is a test bit, and must be left at logic 0. Protocol. Bit PROT is set if the protocol is T = 1 (asynchronous) and bit PROT = 0 if the protocol is T = 0. Transmit/Receive. Bit T/R is set by software for transmission mode. A change from logic 0 to 1 will set bit TBE in register USR. Bit T/R is automatically reset by hardware if bit LCT has been used before transmitting the last character. Last Character to Transmit. Bit LCT is set by software before writing the last character to be transmitted in the UTR. It allows automatic change to reception mode. It is reset by hardware at the end of a successful transmission. When LCT is being reset, the bit T/R is also reset and the ISO 7816 UART is ready for receiving a character. Software convention setting. Bit SS is set by software before ATR for automatic convention detection and early answer detection. It is automatically reset by hardware at 10.5 ETU after reception of the initial character. Convention. Bit CONV is set if the convention is direct. Bit CONV is either automatically written by hardware according to the convention detected during ATR, or by software if the bit AUTOCONV in register UCR2X is set. DESCRIPTION 6 FIP 5 FC 4 PROT 3 T/R 2 LCT 1 SS 0 CONV

8.2.3.5

Clock conguration registers
The Clock Configuration Registers (CCR1, CCR2 and CCR3) relate the clock signals: For cards 1 and 2, register CCRx defines the clock for the selected card For cards 1, 2 and 3, register CCRx defines the clock to the ISO UART. It should be noted that, if bit CKU in the prescaler register of the selected card (register UCR2) is set, then the ISO UART is clocked at twice the frequency of the card, which allows baud rates not foreseen in ISO 7816 norm to be reached. Table 25 Registers CCR1, CCR2 and CCR3 (address 01H; read and write); note CC7 Note 1. Register value at reset: all relevant bits are cleared after reset. 6 CCSHL 4 CST 3 SC 2 ACACAC0
Table 26 Description of CCRx bits BIT SYMBOL CC7 CC6 SHL CST not used not used DESCRIPTION
Stop HIGH or LOW. If bit CST = 1, then the clock is stopped at LOW level if bit SHL = 0, and at HIGH level if bit SHL = 1. Clock stop. In the case of an asynchronous card, bit CST denes whether the clock to the card is stopped or not; if bit CST is reset, then the clock is determined by bits AC0, AC1 and AC2. Synchronous clock. In the event of a synchronous card, then contact CLK is the copy of the value of bit SC; in reception mode, the data from the card is available to bit UR0 after a read operation of register URR; in transmission mode, the data is written on the I/O line of the card when register UTR has been written to and remains unchanged when another card is selected. Alternating clock. All frequency changes are synchronous, thus ensuring that no spikes or unwanted pulse widths occur during changes. AC1 AC1 AC1

1 f 2 int

2 to 0
CLOCK FREQUENCIES (ASYNCHRONOUS CARD) fXTAL

1 2fXTAL 4fXTAL 8fXTAL

Clock switching constraints: fint is the frequency delivered by the internal oscillator In case of fCLK = fXTAL, the duty cycle must be ensured by the incoming clock signal on pin XTAL1 When switching from 1nfXTAL to 12fint or vice verse, only bit AC2 must be changed (bits AC1 and AC0 must remain the same). When switching from 1nfXTAL or 12fint to clock stopped or vice verse, only bits CST and SHL must be changed When switching from 1nfXTALto 12fint or vice verse, a delay can occur between the command and the effective frequency change on CLK (the fastest switching time is from 12fXTAL to 12fint or vice verse, the best for duty cycle is from 18fXTAL to 12fint or vice verse) It is necessary to survey the bit CLKSW in register MSR before re-transmitting commands to the card.
8.2.3.6 Power control registers
The Power Control Registers (PCR1 and PCR2): Start or stop card sessions Read from or write to auxiliary card contacts C4 and C8 Are available only for cards 1 or 2. To deactivate the card, only bit START should be reset. Table 27 Registers PCR1 and PCR2 (address 07H; read and write) 7 PCR7 Note 1. Register value at reset: all relevant bits are cleared after reset. Table 28 Description of PCRx bits BIT SYMBOL PCR7 PCR6 C8 C4 1V8 RSTIN 3V/5V START not used not used Contact 8. When writing to register PCR, pin C8 will output the value of bit C8. When reading from register PCR, bit C8 will store the value on pin C8. Contact 4. When writing to register PCR, pin C4 will output the value of bit C4. When reading from register PCR, bit C4 will store the value on pin C4. 1.8 V cards. If bit 1V8 is set, then VCC = 1.8 V: it should be noted that no specication is guaranteed with this VCC voltage when the supply voltage VDD is inferior to 3 V Reset bit. When the card is activated, pin RST is the copy of the value written in bit RSTIN. 3 or 5 V cards. If bit 3V/5V = 1, then VCC = 3 V; if bit 3V/5V = 0, then VCC = 5 V. Start. If the microcontroller sets bit START = 1, then the selected card is activated (see Section 8.6); if the microcontroller resets bit START = 0, then the card is deactivated (see Section 8.7). Bit START is automatically reset in case of emergency deactivation. To deactivate the card, only bit START should be reset. DESCRIPTION 6 PCRCC1VRSTIN 1 3V/5V 0 START

handbook, full pagewidth V
VDD Vth2 CDELAY tw RSTOUT
INT Status read Power-on Supply dropout Reset by CDELAY Power-off

FCE683

Fig.13 Voltage supervisor.
8.4 Step-up converter 8.5 ISO 7816 security
Except for the VCC generator and the other cards contact buffers, the whole circuit is powered by VDD and VDDA. If the supply voltage is 2.5 V, then a higher voltage is needed for the ISO contacts supply. When a card session is requested by the microcontroller, the sequencer first enables the step-up converter (switched capacitors type) which is clocked by an internal oscillator at a frequency of approximately 2.5 MHz. Supposing that VCC is the maximum of VCC1 and VCC2, then the possible situations are: VCC = 5 V For VDD = 3 V the step-up converter acts as a voltage tripler with regulation of VUP at approximately 5.5 V For VDD = 5 V the step-up converter acts as a voltage doubler with regulation of VUP at approximately 5.5 V VCC = 3 V For VDD = 3 V the step-up converter acts as a voltage doubler with regulation of VUP at approximately 4.0 V For VDD = 5 V the step-up converter acts as a voltage follower and VDD is applied to VUP VCC = 1.8 V The step-up converter acts as a voltage follower for any value of VDD. The recognition of the supply voltage is done by the TDA8007BHL/C at approximately 3.5 V. The output voltage VUP is fed to the VCC generators. VCC and CGND are used as a reference for all other card contacts.
The correct sequence during activation and deactivation of the cards is ensured by two specific sequencers, the clock is defined by a division ratio of the internal oscillator. Activation (bit START = 1 in registers PCR1 or PCR2) is only possible if the card is present (pin PRES is active HIGH with an internal current source to ground) and if the supply voltage is correct (voltage supervisor not active). The presence of the cards is signalled to the microcontroller by register HSR. Bits PR1 or PR2 in register MSR are set if card 1 or 2 is present. Bits PRL1 or PRL2 are set if pins PRES1 or PRES2 have been toggled. During a session, the sequencer performs an automatic emergency deactivation on one card in the event of card take-off, or short-circuit. Both cards are automatically deactivated in the event of a supply voltage drop, or overheating. Register HSR is updated and the INT line falls so that the system microcontroller is aware of what happened.

8.6 Activation sequence

3. Pin I/O rises to VCC (t3); pins C4 and C8 also rise if bits C4 and C8 within register PCR have been set to logic 1 (integrated 14 k pull-up resistors to VCC). 4. Clock pulse CLK is sent to the card (t4) and pin RST is enabled. 5. After a number of CLK pulses that can be counted with the time-out counter, bit RSTIN may be set by software and pin RST will then rise to VCC. 6. The sequencer is clocked by 164fint which leads to a time interval of t = 25 s (typical). Thus: t1 = 0 to 164t t2 = t1 + 32t t3 = t1 + 72t t4 = t1 + 4t.
When the cards are inactive, pins VCC, CLK, RST, C4, C8 and I/O are at LOW level and have a low-impedance with respect to ground. The step-up converter is stopped. When everything is satisfactory (voltage supply, card present and no hardware problems), the system microcontroller may initiate an activation sequence of a present card. After selecting the card and leaving the UART reset mode, and then configuring the necessary parameters for the counters and the UART, bit START can be set within register PCR at t0 (see Fig.14): 1. The step-up converter is started (t1); if one card was already active, then the step-up converter was already on and nothing more occurs at this step. 2. Pin VCC starts rising (t2) from 0 to 3 or 5 V with a controlled rise time of 0.17 V/s (typical).

VUP VCC I/O

RST t0 t1 t2 t3 t4 = tact ATR

FCE684

Fig.14 Activation sequence.
8.7 Deactivation sequence Thus: t11 = t10 + 164t t12 = t11 + 12t t13 = t11 + t t14 = t11 + 32t t15 = t11 + 72t
When the session is completed, the microcontroller resets bit START at t10. The circuit then executes an automatic deactivation sequence (see Fig.15): 1. The card is reset by signal RST = LOW (t11). 2. Clock pulse CLK is stopped (t12). 3. Pins I/O, C4 and C8 fall to 0 V (t13). 4. Pin VCC falls to 0 V with typical 0.17 V/s slew rate (t14). 5. The step-up converter is stopped (t15) and pins CLK, RST, VCC and I/O become low-impedance to ground, if both cards are inactive.
tde = time that VCC needs to decrease to less than 0.4 V.

RST CLK

VCC VUP t10 t11 t12 tde t13 t14 t15

FCE685

Fig.15 Deactivation sequence.
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD VDDA Vn supply voltage analog supply voltage input voltage on pins SAM, SAP, SBM, SBP and VUP on all other pins Ptot Tstg Tj Ves total power dissipation storage temperature junction temperature electrostatic discharge voltage human body model; note 1 on pins I/O1, I/O2, VCC1, VCC2, RST1, RST2, CLK1, CLK2, CGND1, CGND2, PRES1 and PRES2 on pins C41, C42, C81 and C82 on all other pins Note 1. Human body model as defined in JEDEC Standard JESD22-A114-B, dated June 2000. 10 HANDLING Tamb = 25 to +85 C 0.5 0.6 PARAMETER CONDITIONS MIN. 0.5 0.5
MAX. +6.5 +6.5 +7.5 VDD + 0.++6

UNIT V V V V mW C C kV

Clock output to the cards: pins CLK1 and CLK2 output voltage in inactive mode output current in inactive mode LOW-level output voltage HIGH-level output voltage rise time fall time clock frequency 0.1 0.0.3 VCC 1.55
Card supply output voltage: pins VCC1 and VCC2; note 1 Vo(inactive) Io(inactive) output voltage in inactive mode output current in inactive mode no load Io(inactive) = 1 mA Vo = 0 V 0.1 0.V V mA

SYMBOL VCC

PARAMETER output voltage in active mode
CONDITIONS 5 V card; ICC < 65 mA 3 V card; ICC < 50 mA 1.8 V card; ICC < 30 mA 5 V card; current pulses of 40 nC with I < 200 mA, t < 400 ns and f < 20 MHz 3 V card; current pulses of 24 nC with I < 200 mA, t < 400 ns and f < 20 MHz

MIN. 4.75 2.78 1.65 4.6

TYP. 1.8

MAX. 5.25 3.22 1.95 5.4

UNIT V V V V
1.8 V card; current pulses of 1.nC with I < 200 mA, t < 400 ns and f < 20 MHz ICC output current 5 V card; VCC = 0 to 5 V 3 V card; VCC = 0 to 3 V 1.8 V card; VCC = 0 to 1.8 V ICC1 + ICC2 SR sum of both output currents slew rate up or down; maximum capacitance of 300 nF 0.05

0.16

mA mA mA mA V/s
Data lines: pins I/O1 and I/O2; note 2 Rpu Vo(inactive) Io(inactive) internal pull-up resistance output voltage in inactive mode output current in inactive mode between pin I/O and VCC no load Io(inactive) = 1 mA Vo = 0 V 14 17 0.1 0.k V V mA

Congured as output

VOL VOH to(r), to(f) LOW-level output voltage HIGH-level output voltage output transition time (rise and fall time) IOL = 1 mA IOH < 20 A IOH < 40 A for 5 and 3 V cards CL 30 pF 0 0.8VCC 0.75VCC 0.3 V VCC + 0.25 V VCC + 0.25 V 0.1 s

Congured as input

VIL VIH IIL ILIH ti(r), ti(f) LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input leakage current input transition time (rise and fall time) VIL = 0 V VIH = VCC CL 30 pF 0.3 1.5 +0.8 VCC 1.2 V V A A s

SYMBOL

TYP.
Auxiliary cards contacts: pins C41, C81, C42 and C82; note 3 Vo(inactive) Io(inactive) tW(pu) Rint(pu) fmax VOL VOH to(r), to(f) output voltage in inactive mode output current in inactive mode active pull-up pulse width internal pull-up resistance maximum frequency between pins C4 or C8 and VCC on card contact pins no load Io(inactive) = 1 mA Vo = 0 V 0 0.8VCC 0.75VCC 0.1 0.V V mA ns k MHz

LOW-level output voltage HIGH-level output voltage output transition time (rise and fall time) IOL = 1 mA IOH < 20 A IOH < 40 A for 5 and 3 V cards CL = 30 pF 0.3 V VCC + 0.25 V VCC + 0.25 V 0.1 s
VIL VIH IIL ILIH ti(r), ti(f) Timing tact tde activation sequence duration deactivation sequence duration see Fig.14 see Fig.15 s s LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input leakage current input transition time (rise and fall time) VIL = 0 V VIH = VCC CL = 30 pF 0.3 1.5 +0.8 VCC 1.2 V V A A s
Protection and limitation ICC(sd) II/O(lim) ICLK(lim) IRST(sd) IRST(lim) Tsd shutdown and limitation current at pin VCC limitation current on pin I/O limitation current on pin CLK shutdown current on pin RST limitation current on pin RST shutdown temperature +15 +70 +20 mA mA mA mA mA C

CONDITIONS

Card presence inputs: pins PRES1 and PRES2 VIL VIH ILIL ILIH LOW-level input voltage HIGH-level input voltage LOW-level input leakage current HIGH-level input leakage current VIL = 0 V VIH = VDD 0.3VDD V V A A 0.7VDD
Bidirectional data bus: pins D0 to D7
VIL VIH ILIL ILIH CL VOL VOH to(r), to(f) LOW-level input voltage HIGH-level input voltage LOW-level input leakage current HIGH-level input leakage current load capacitance 0.7VDD IOL = 5 mA IOH = 5 mA CL = 50 pF 0.8VDD 0.3VDD +20 +V V A A pF
LOW-level output voltage HIGH-level output voltage output transition time (rise and fall time) 0.2VDD 25 V V ns
Logic inputs: pins ALE, AD0, AD1, AD2, AD3, INTAUX, CS, RD and WR VIL VIH ILIL ILIH CL Rint(pu) fmax VIL VIH ILIH IIL ti(r), ti(f) LOW-level input voltage HIGH-level input voltage LOW-level input leakage current HIGH-level input leakage current load capacitance 0.3 0.7VDD between pin I/OAUX and VDD on pin I/OAUX 11 0.3 0.7VDD 20 VIL = 0 V CL = 30 pF 14 0.3VDD VDD + 0.3 +20 +V V A A pF
Auxiliary input and output: pin I/OAUX; note 4 internal pull-up resistance maximum frequency k MHz
LOW-level input voltage HIGH-level input voltage HIGH-level input leakage current LOW-level input current input transition time (rise and fall time) 0.3VDD VDD + 0.3 +1.2 V V A A s
VOL VOH to(r), to(f) LOW-level output voltage HIGH-level output voltage output transition time (rise and fall time) IOL = 1 mA IOH = 40 A CL = 30 pF 300 0.1 mV s 0.75VDD VDD + 0.25 V
Interrupt line: pin INT (open-drain output) VOH ILIH Notes 1. To meet these specifications, two ceramic multilayer capacitors with low ESR of minimum 100 nF should be used. 2. Pin I/O1 has an integrated 14 k pull-up resistance to VCC1 and pin I/O2 has an integrated 14 k pull-up resistance to VCC2. 3. Pins C41 and C81 have an integrated 10 k pull-up resistance to VCC1 and pins C42 and C82 have an integrated 10 k pull-up resistance to VCC2. 4. Pin I/OAUX has a 14 k pull-up resistance to VDD. 13 TIMING VDD = 3.3 V; VDDA = 3.3 V; Tamb = 25 C; unless otherwise specied. SYMBOL PARAMETER CONDITIONS MIN. TYP. 50 MAX. UNIT LOW-level output voltage HIGH-level input leakage current IOH = 2 mA 0.V A

Timing for multiplexed bus; see Fig.4 Tcy(XTAL1) tW(ALE) tAVLL t(ALRWL) tW(RD) t(RLDV) t(RWHAH) tW(WR) t(DVWL) XTAL1 cycle time ALE pulse width address valid to ALE LOW ALE LOW to RD or WR LOW RD pulse width RD LOW to data read valid RD or WR HIGH to ALE HIGH WR pulse width data write valid to WR LOW for register URR for other registers 2Tcy(XTAL1) ns ns ns ns ns ns ns ns ns ns
Timing for non-multiplexed bus READ CONTROL; see Fig.5 t1 t2 t3 RD HIGH to CS LOW access time CS LOW to data out valid CS HIGH to data out high-impedance ns ns ns
WRITE CONTROL; see Figs 6 and 7 t4 t5 t6 t7 data valid to end-of-write data hold time RD LOW to CS or WR LOW address stable to CS or WR HIGH ns ns ns ns
Timing for bit CRED READ OPERATIONS IN UART RECEIVE REGISTER; see Fig.9 tW(RD) tRD(URR) tSB(FE) tSB(RBF) tW(WR) tWR(UTR) tW(WR) tWR(TOC) Note 1. PSC is the programmed prescaler value (31 or 32). RD pulse width RD LOW to bit CRED = 1 set time bit FE set time bit RBF 10 tW(RD) + 2Tcy(CLK) 10.5 10.5 tW(RD) + 3Tcy(CLK) tW(WR) + 3Tcy(CLK) 2 ----------PSC ns ns ETU ETU
WRITE OPERATIONS IN UART TRANSMIT REGISTER; see Fig.10 WR pulse width WR LOW to I/O LOW 10 tW(WR) + 2Tcy(CLK) 10 note ----------PSC ns ns
WRITE OPERATIONS IN TIME-OUT CONFIGURATION REGISTER; see Fig.11 WR pulse width WR LOW to bit CRED = 1 ns ETU
VDD C6 C4 C3 C2 C1 C51 C61 C71 C81 C8 C7 C6 C5 C11 C21 C31 C41 DELAY XTAL1 XTALnF CnF RSTOUT I/OAUX I/O1 C81 K1 CARD_READ_LM01 U1 K2 PRES1 C41 CGNDAD2 ADINTAUX 41 INT 40 ALE 39 CS 38 WR 37
14 APPLICATION INFORMATION
CpF Y1 CpF BP1 VDD P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 PSEN ALE EA P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 VCC V SS XTAL19 XTAL23 P3.17 P3.16 P3.15 P3.14 P3.13 P3.12 P3.11 89C51 P3.10 RST P1.33 P1.34 P1.35 P1.36 P1.37 P1.38 P1.39 P1.40 C15 CnF VDD CF (16 V) 100 nF VDD

AD0 45

RD D7 D6 D5 D4 D3 D2 D0 P0(7:0) VDD 1 0
Normally closed switch CnF
7 CLKVCCRSTI/OCPRES2 CCGND2
C4 C3 C2 C1 C51 C61 C71 C81
C8 C7 C6 C5 C11 C21 C31 C41
CLKVCCRSTGND 19 VUP 20 SAP 21 SBP 22 VDDA 23 SBM 24

DVDD 27 SAM 26 AGND 25

FCE690

CnF CnF CnF CnF

K1 CARD_READ_LM01 U2 K2

CF (16 V) VDD

Fig.16 Application diagram.
15 PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

SOT313-2

(A 3) Lp L detail X
w M pin 1 index 12 ZD bp D HD w M B v M B v M A 13 bp

2.5 scale

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.0o

TOC VALUE 00H 05H 61H

TOC VALUE 75H
OPERATING MODE Counter 1 is an 8-bit auto-reload counter, and counters 3 and 2 form a 16-bit counter. Counter 1 starts counting the content of register TOR1 on the rst START bit (reception or transmission) detected on pin I/O after 75H is written in register TOC. When counter 1 reaches its terminal count, an interrupt is given, bit TO1 in register USR is set, and the counter automatically restarts the same count until it is stopped. Changing the content of register TOR1 during a count is not allowed. Counting the value stored in registers TOR3 and TOR2 is started on the rst START bit detected on pin I/O (reception or transmission) after the value has been written, and then on each subsequent START bit. It is possible to change the content of registers TOR3 and TOR2 during a count; the current count will not be affected and the new count value will be taken into account at the next START bit. The counter is stopped by writing 00H in register TOC. In this conguration, registers TOR3, TOR2 and TOR1 must not be all zero. Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in registers TOR3, TOR2 and TOR1 is started on the rst START bit detected on pin I/O (reception or transmission) after the value has been written, and then on each subsequent START bit. It is possible to change the content of registers TOR3, TOR2 and TOR1 during a count; the current count will not be affected and the new count value will be taken into account at the next START bit. The counter is stopped by writing 00H in register TOC. In this conguration, registers TOR3, TOR2 and TOR1 must not be all zero. Same as value 05H, except that all the counters will be stopped at the end of the 12th ETU following the rst received START bit detected after 85H has been written in register TOC. Same conguration as value 65H, except that counter 1 will be stopped at the end of the 12th ETU following the rst START bit detected after E5H has been written in register TOC. Same conguration as value 71H, except that the 16-bit counter will be stopped at the end of the 12th ETU following the rst START bit detected after F1H has been written in register TOC. Same conguration as value 75H, except the two counters will be stopped at the end of the 12th ETU following the rst START bit detected after F5H has been written in register TOC. Writing to register TOC is not allowed as long as the card is not activated with a running clock. Before restarting the 16-bit counter (counters 3 and 2) by writing 61H or 65H in the TOC; or the 24-bit counter (counters 3, 2 and 1) by writing 68H in the TOC; it is mandatory to stop them by writing 00H in the TOC. Detailed examples of how to use these specific timers can be found in application note AN10125.

85H E5H F1H F5H

The time-out counter is very useful for processing the clock counting during ATR, the Work Waiting Time (WWT) or the waiting times defined in protocol T = 1. It should be noted that the 200 and 384 clock counter used during ATR is done by hardware when the start session is set, specific hardware controls the functionality of BGT in T = 1 and T = 0 protocols and a specific register is available for processing the extra guard time.
8.1.4 ISO 7816 UART REGISTERS

8.1.4.1

UART receive register
Table 10 Register URR (address 0DH; read only); note UR7 Note 1. Register value at reset: all bits are cleared after reset. When the microcontroller wants to read data from the card, it reads it from the UART Receive Register (URR) in direct convention: With a synchronous card, only D0 is relevant and this is a copy of the state of the selected card I/O When needed, this register may be tied to a FIFO whose length n is programmable between 1 and 8; if n > 1, no interrupt is given until the FIFO is full, then the controller may empty the FIFO when required When the FIFO is full, bit RBF in the status register USR is set; this bit is reset when at least one character has been read from URR When the FIFO is empty, bit FE is set in the status register MSR as long as no character has been received With a parity error: In protocol T = 0; the received byte is not stored in the FIFO and the error counter is incremented. The error counter is programmable between 1 and 8. When the programmed number is reached, the bit PE is set in the status register USR and INT0 falls LOW. The error counter must be reprogrammed to the desired value after its count has been reached In protocol T = 1; the character is loaded in the FIFO and the bit PE is set, whatever the programmed value in parity error counter. 6 URURURURURURUR0

8.1.4.2

UART transmit register
Table 11 Register UTR (address 0DH; write only); note UT7 Note 1. Register value at reset: all bits are cleared after reset. When the microcontroller wants to transmit a character to the selected card, it writes the data in direct convention in the UART Transmit Register (UTR). The transmission: Starts at the end of writing (on the rising edge of signal WR) if the previous character has been transmitted and if the extra guard time has expired Starts at the end of the extra guard time if this one has not expired Does not start if the transmission of the previous character is not completed With a synchronous card (bit SAN within register UCR2 is set), only signal D0 is relevant and is copied on pin I/O of the selected card. 6 UTUTUTUTUTUTUT0

FE BGT

SYMBOL TBE/RBF
DESCRIPTION Transmit buffer empty/receive buffer full. Bit TBE/RBF = 1 when: Changing from reception mode to transmission mode A character has been transmitted by the ISO 7816 UART The reception FIFO is full. Bit TBE/RBF = 0 after power-on or after one of the following: When bit RIU is reset When a character has been written to register UTR When at least one character has been read in the FIFO When changing from transmission mode to reception mode.

bit TBE

WR tW(WR) bit CRED tWR(UTR)

FCE902

Fig.5 Minimum time between two write operations in UTR.

bit RBF

bit FE tSB(FE) INT tSB(RBF) RD tW(RD) bit CRED tRD(URR) tRD(URR)

FCE903

Fig.6 Minimum time between two read operations in URR.
handbook, full pagewidth WR

tW(WR) bit CRED tWR(TOC)

FCE904
Fig.7 Minimum time between two write operations in TOC.

8.1.4.4

FIFO control register
The FIFO Control Register (FCR) relates the parity error count and the FIFO length. Table 14 Register FCR (address 0CH; write only); note FC7 Note 1. Register value at reset: all relevant bits are cleared after reset. Table 15 Description of FCR bits. BIT to 4 SYMBOL FC7 PEC2 to 0 Not used. Parity Error Count. Bits PEC2, PEC1 and PEC0 determine the number of allowed repetitions in reception or in transmission before setting bit PE in register USR and pulling pin INT0 to LOW level. The value 000 indicates that, if only one parity error has occurred, bit PE is set; the value 111 indicates that bit PE will be set after 8 parity errors. In protocol T = 0: If a correct character is received before the programmed error number is reached, the error counter will be reset If the programmed number of allowed parity errors is reached, bit PE in register USR will be set as long as register USR has not been read If a transmitted character has been NAKed by the card, then the TDA8008 will automatically re-transmit it a number of times equal to the value programmed in bits PEC2, PEC1 and PEC0; the character will be present at 15 ETU In transmission mode, if bits PEC2, PEC1 and PEC0 are logic 0, then the automatic re-transmission is invalidated; the character manually rewritten in register UTR will start at 13.5 ETU. In protocol T = 1: The error counter has no action: bit PE is set at the first incorrectly received character. to 0 FC3 FL2 to 0 Not used. FIFO length. Bits FL2, FL1 and FL0 determine the depth of the FIFO: 000 = length = length 8. DESCRIPTION 6 PECPECPECFCFLFLFL0
8.1.4.5 UART status register
Bit TBE/RBF is reset 3 clock cycles after a data write to register UTR, or 3 clock cycles after a data read from register URR, or when changing from transmission mode to reception mode if the FIFO register had not been left full when going to transmission. In order to avoid counting these clock cycles, the bit CRED in register MSR may be used (see Table 12). If bit LCT is used for transmitting the last character, then bit TBE is not set at the end of the transmission.

The UART Status Register (USR) is used by the embedded microcontroller to monitor the activity of the ISO 7816 UART and that of the time-out counter. If any of the status bits FER, OVR, PE, EA, TO1, TO2 or TO3 are set then pin INT0 will go LOW. The bit having caused the interrupt is reset 2 s after the rising edge of RD during a read operation of register USR. If bit TBE/RBF is set, and if the mask bit DISTBE/RBF within register UCR2 is not set, then pin INT0 will also be LOW. Table 16 Register USR (address 0EH; read only); note TO3 Note 1. Register value at reset: all bits are cleared after reset. Table 17 Description of USR bits. BIT SYMBOL TO3 TO2 TO1 EA 6 TOTOEA
DESCRIPTION Time-out counter 3. Bit TO3 is set when counter 3 has reached its terminal count. Time-out counter 2. Bit TO2 is set when counter 2 has reached its terminal count. Time-out counter 1. Bit TO1 is set when counter 1 has reached its terminal count. Early answer. Bit EA = 1 if the rst START bit on pin I/O during ATR has been detected between the rst 200 and 384 clock pulses with RST LOW (all activities on pin I/O during the rst 200 clock pulses with RST LOW are not taken into account) and before the rst 384 clock pulses with RST HIGH. These two features are re-initialized at each toggling of RST. Parity error. In protocol T = 0, bit PE = 1 if the ISO 7816 UART has detected a number of received characters with parity errors equal to the number written in bits PEC2, PEC1 and PEC0, or if a transmitted character has been NAKed by the card a number of times equal to the value programmed in bits PEC2, PEC1 and PEC0. It is set at 10.5 ETU in the reception mode and at 11.5 ETU in the transmission mode. In protocol T = 0, a character received with a parity error is not stored in register FIFO (the card should repeat this character). In protocol T = 1, a character with a parity error is stored in the FIFO and the parity error counter is not active.

OVR FER

Overrun. Bit OVR = 1 if the UART has received a new character whilst register FIFO was full. In this case, at least one character has been lost. Framing error. Bit FER = 1 when pin I/O was not in the high-impedance state at 10.25 ETU after a START bit. It is reset when register USR has been read-out.
DESCRIPTION Transmission buffer empty/reception buffer full. Bits TBE and RBF share the same bit within register USR: when in transmission mode the relevant bit is TBE; when in reception mode it is RBF. Bit TBE = 1 when the ISO 7816 UART is in transmission mode and when the embedded microcontroller may write the next character to transmit in register UTR. It is reset when the embedded microcontroller has written data in the transmit register or when bit T/R within register UCR1 has been reset either automatically or by software. After detection of a parity error in transmission, it is necessary to wait 13.5 ETU before rewriting the character that has been NAKed by the card. (Manual mode, register FCR; see Table 29). Bit RBF = 1 when register FIFO is full. The embedded microcontroller may read some of the characters in register URR, which clears bit RBF.

The Power Control Registers (PCR1 and PCR2): Start or stop card sessions Read from or write to auxiliary card contacts C4 and C8 Are available only for cards 1 or 2. Table 27 Registers PCR1 and PCR2 (address 07H; read and write) 7 PCRPCRCC1VRSTIN 1 3V/5V 0 START
Register value at reset: all relevant bits are cleared after reset. Table 28 Description of PCRx bits BIT SYMBOL PCR7 PCR6 C8 C4 1V8 RSTIN 3V/5V START not used not used Contact 8. When writing to register PCR, pin C8 will output the value of bit C8; when reading from register PCR, bit C8 will store the value on pin C8. Contact 4. When writing to register PCR, pin C4 will output the value of bit C4; when reading from register PCR, bit C4 will store the value on pin C4. 1.8 V cards. If bit 1V8 is set, then VCC = 1.8 V; no specication is guaranteed with this VCC level when the supply voltage VDD is inferior to 3 V. Reset bit. When the card is activated, pin RST is the copy of the value written in bit RSTIN. 3 or 5 V cards. If bit 3V/5V = 1, then VCC = 3 V; if bit 3V/5V = 0, then VCC = 5 V. Start. If the embedded microcontroller sets bit START = 1, then the selected card is activated (see Section 8.7); if the embedded microcontroller resets bit START = 0, then the card is deactivated (see Section 8.8); bit START is automatically reset in case of emergency deactivation. DESCRIPTION
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8.1.5.7

Register Summary

2003 Jul 28 29

Table 29 Register summary ADDR 09 0A 0B 0C 0C 0D 0D 0E 0F Notes 1. X = undefined; u = no change. 2. PDR, GTR, UCR1, UCR2, CCR and PCR vary according to the card selected. NAME CSR CCR(2) PDR(2) UCR2(2) GTR(2) UCR1(2) PCR(2) TOC TOR1 TOR2 TOR3 FCR MSR URR UTR USR HSR R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W W R R W R R not used PD7 ENINT1 GT7 not used not used TOC7 TOL7 TOL15 TOL23 not used CLKSW UR7 UT7 TO3 not used not used PD6 DISTBE/ RBF GT6 FIP not used TOC6 TOL6 TOL14 TOL22 PEC2 FE UR6 UT6 TO2 PRTL0 SHL PD5 DISAUX GT5 FC C8 TOC5 TOL5 TOL13 TOL21 PEC1 BGT UR5 UT5 TO1 PRTL0 CST PD4 ENRX GT4 PROT C4 TOC4 TOL4 TOL12 TOL20 PEC0 CRED UR4 UT4 EA SUPL 3 RIU SC PD3 SAN GT3 T/R 1V8 TOC3 TOL3 TOL11 TOL19 not used PR2 UR3 UT3 PE PRLSC3 AC2 PD2 AUTOCONV GT2 LCT RSTIN TOC2 TOL2 TOL10 TOL18 FL2 PR1 UR2 UT2 OVR PRLSC2 AC1 PD1 CKU GT1 SS 3V/5V TOC1 TOL1 TOL9 TOL17 FL1 INTAUX UR1 UT1 FER INTAUXL 0 SC1 AC0 PD0 PSC GT0 CONV START TOC0 TOL0 TOL8 TVOL16 FL0 UR0 UT0 TBE/RBF PTL VALUE AT RESET XVALUE(1) WHEN RIU = uuuu uuuu uuuu uuuu uuuu uuuu uuuu Xuuu 00uu uuuu uuuu uuuu uuuu uuuu uuuu

XXXXuu uuuu

X000 X000 Xuuu Xuuu XXuuu uuuu
TBE/RBF 0101 XXX0 u1u1 uuu0

8.2 Supply and reset

The voltage supervisor generates an ALARM pulse when VDDA is too low to ensure proper operation. The pulse length is defined by an external capacitor tied to pin CDELAY and is typically 1 ms per 2 nF. The ALARM pulse may be used as a reset pulse by the embedded microcontroller (pin RSTOUT = HIGH). It also can be used when VDDA is too low to ensure proper operation can be used to block any spurious noise on card contacts during the embedded microcontroller reset, or to force an automatic deactivation of the contacts in the event of a supply drop-out (see Sections 8.7 and 8.8). A HIGH-level on pin RESET may also be used to reset the whole chip as power-on is detected. After power-on, or after a voltage drop, bit SUPL is set within register HSR and remains set until HSR is read-out outside the ALARM pulse. Signal INT0 is LOW for the duration that RSTOUT is active.
The TDA8008 operates within a supply voltage range of 2.7 to 6 V. The supply pins are VDDD, VDDA, VDDP, GNDP, GNDD and GNDA. Pins VDDA and GNDA supply the analog drivers to the cards and have to be decoupled externally because of the large current spikes that the cards and the step-up converter can create. VDDA may be different from VDDD. The step-up converter is supplied via pins VDDP and GNDP, and the rest of the chip is supplied via pins VDDD and GNDD. An integrated spike killer ensures that the contacts to the cards remain inactive during power-up and power-down. An internal voltage reference is generated for use within the step-up converter, the voltage supervisor and the VCC generators.
handbook, full pagewidth V
VDD Vth2 CDELAY tw RSTOUT
INT Status read Power-on Supply dropout Reset by CDELAY Power-off

FCE683

Fig.9 Voltage supervisor.

8.3 Step-up converter

During a session, the sequencer performs an automatic emergency deactivation on one card in the event of card take-off, or short-circuit. Both cards are automatically deactivated in the event of a supply voltage drop or overheating. Register HSR is updated and the INT0 line falls, so that the embedded microcontroller is aware of what happened. 8.5 Power reduction modes
Except for the VCC generator and the other cards contact buffers, the whole circuit is powered by VDD and VDDA. If the supply voltage is 2.7 V, then a higher voltage is needed for the ISO contacts supply. When a card session is requested by the embedded microcontroller, the sequencer first enables the step-up converter (a switched capacitors type) which is clocked by an internal oscillator at a frequency of approximately 2.5 MHz. Supposing that VCC is the maximum of VCC1 and VCC2, then the possible situations are: VCC = 3 V For VDD = 3 V the step-up converter acts as a voltage doubler with regulation of VUP at approximately 4.0 V For VDD = 5 V the step-up converter acts as a voltage follower and VDD is applied to VUP. VCC = 5 V For VDD = 3 V the step-up converter acts as a voltage tripler with regulation of VUP at approximately 5.5 V For VDD = 5 V the step-up converter acts as a voltage doubler with regulation of VUP at approximately 5.5 V. VCC = 1.8 V The step-up converter acts as a voltage follower for any value of VDD. The recognition of the supply voltage is done by the TDA8008 at approximately 3.5 V. Output voltage VUP is fed to the VCC generators. VCC and GNDC are used as a reference for all other card contacts. 8.4 ISO 7816 security

8.9.1.3

Port 2
Port 2 (P27 to P20) is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have logic 1s written to them are pulled HIGH by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are being pulled LOW externally will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX at DPTR). In this application it uses strong internal pull-ups when emitting logic 1s. During accesses to external data memory that use 8-bit addresses (MOV at Ri), Port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high-order address bits during EPROM programming and verification.
XTAL1 and XTAL2 are, respectively, the input and output of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum HIGH and LOW times specified in the data sheet must be observed. 8.9.3 RESET
A reset is accomplished by holding the RESET pin HIGH for at least two machine cycles (24 oscillator periods) while the oscillator is running. To ensure a good Power-on reset, the RESET pin must be HIGH long enough to allow the oscillator time to start-up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on pins VDDD, VDDA, VDDP and RESET must come up at the same time for a proper start-up. Ports 1, 2 and 3 will be driven to their reset condition asynchronously when a voltage above VIH1 (min.) is applied to RESET.

8.9.4 LOW POWER MODES

A hardware reset, an external interrupt or a signal received on pin RX can be used to exit from power-down. RESET redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. With INT0, INT1 or RX, the corresponding bits in the interrupt enable register must be enabled. Within the INT0 interrupt service routine, the microcontroller must read the hardware status register (address 0FH) and/or the UART status register (address 0EH) by means of MOVX instructions in order to determine the cause of the interrupt and to reset the interrupt source. For enabling a wake-up using INT1, the bit ENINT1 within register UCR2 must be set. For enabling a wake-up using RX, the bits ENINT1 and ENRX within register UCR2 must be set. An integrated delay counter holds INT0 and INT1 LOW long enough to allow the oscillator to restart properly, so a falling edge on pins RX, INT0 and INT1 is enough to wake-up the whole circuit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power-down mode.

SM1 SM2

REN TB8 RB8 Tl
Note 1. Bit SMOD0 is located in register PCON.
8.9.9.1 Automatic address recognition
In the example shown in Table 44, SADDR is the same for both slaves and the SADEN data differentiates between them. Slave 0 requires a logic 0 in bit 0 and it ignores bit 1. Slave 1 requires a logic 0 in bit 1 and bit 0 is ignored. A unique address for slave 0 would be since slave 1 requires a logic 0 in bit 1. A unique address for slave 1 would be since a logic 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = logic 0 for slave 0 and bit 1 = logic 0 for slave 1. Thus, both could be addressed with 1100 0000. In a more complex system, the example shown in Table 45 could be used to select slaves 1 and 2 while excluding slave 0. In this example, the differentiation between the three slaves is in the lower of the three address bits. Slave 0 requires that bit 0 = logic 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = logic 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = logic 0 and its unique address is 1110 0011. To select slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = logic 1 to exclude slave 2. The broadcast address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as dont cares. In most cases, interpreting the dont cares as logic 1s, the broadcast address will be FFH. Table 45 Automatic addressing example 2 REGISTER Slave 0 SADDR SADEN Given address Slave 1 SADDR 1110 0X0X SADEN Given address Slave 2 SADDR 1110 00XX SADEN Given address Note 1. X = dont care. 1110 0XX0 ADDRESS(1)
Automatic address recognition is a feature that allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons (see Fig.17). This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. It is enabled by setting the bit SM2 in register SCON. In 9-bit UART Modes 2 and 3, the Receive Interrupt flag (RI) will be set automatically when the received byte contains either the given address or the broadcast address. The 9-bit mode requires that the 9th information bit is a logic 1 to indicate that the received information is an address and not data. The 8-bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid STOP bit following the 8 address bits and the information is either a given or a broadcast address. Mode 0 is the shift register mode and SM2 is ignored. Using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. All of the slaves may be contacted by using the broadcast address. Special function registers are used to define the slaves address (register SADDR) and the address mask (register SADEN). Register SADEN is used to define which bits in register SADDR are to be used and which bits are dont care. The SADEN mask can be logically ANDed with register SADDR to create the given address which the master will use for addressing each of the slaves. Use of the given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme. Table 44 Automatic addressing example 1 REGISTER Slave 0 SADDR SADEN Given address Slave 1 SADDR SADEN Given address Note 1. X = dont care. 2003 Jul 1100 000X 1100 00X0 ADDRESS(1)

8.9.14.3

Reading the signature bytes
The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P36 and P37 need to be pulled to a logic LOW. The values are: (030H) = 15H indicates manufactured by Philips (031H) = CBH indicates TDA8008 (060H) = NA.

8.9.14.4

Security bits
With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the internal memory, EA is latched on reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. When all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled.

8.9.14.5

Encryption array
There are 64 bytes of encryption array and these are all initially unprogrammed (all at logic 1).
(1) Improved Quick-Pulse Programming is a trademark of the Intel Corporation.
8.9.14.6 EPROM programming modes
Table 57 EPROM programming VPP = 12.75 V 0.25 V; during programming and verification supply voltage VDD = 5 V 10% INPUTS FOR PROGRAMMING(1) MODE RESET Read signature Program code data Verify code data Program encryption table Program security bit 1 Program security bit 2 Program security bit 3 Notes 1. For each input, 0 indicates valid LOW and 1 indicates valid HIGH 2. ALE/PROG receives five programming pulses for code data (also for user array; five pulses for encryption or security bits) while VPP is held at 12.75 V. Each programming pulse is LOW for 100 s 10 s and HIGH for a duration of 10 s minimum. Table 58 Security bit programming SECURITY BITS(1) PROGRAM PROTECTION SB1 U P SB2 U U SB3 U U no program security features are enabled (code verify will continue to be encrypted by the encryption array, if programmed) MOVC instructions executed from external program memory are disabled by fetching code bytes from internal memory, EA is sampled and latched on RESET and further programming of the EPROM is disabled MOVC instructions executed from external program memory are disabled by fetching code bytes from internal memory, EA is sampled and latched on RESET and further programming of the EPROM is disabled; code verify is disabled MOVC instructions executed from external program memory are disabled by fetching code bytes from internal memory; EA is sampled and latched on RESET and further programming of the EPROM is disabled; external execution is disabled 1 PSEN 0 ALE/PROG(2) 0 EA/VPP 1 VPP 1 VPP VPP VPP VPP P2.P2.P3.P3.0 1

0.1 0.0.3 VCC + 0.25 VCC + 0.25 +0.8 VCC 600 20

V V mA V V V V V A A

pin I/O congured as an output; 0 IOL = 1 mA pin I/O congured as an output; 0.8VCC IOH < 20 A pin I/O congured as an output; 0.75VCC IOH < 40 A (5 and 3 V cards)
VIL VIH IIL ILIH 2003 Jul 28
LOW-level input voltage HIGH-level input voltage LOW-level input current input leakage current HIGH
pin I/O congured as an input pin I/O congured as an input VIL = 0 V VIH = VCC 58

0.3 1.5

SYMBOL ti(tr), ti(tf) to(tr), to(tf) Rpu
PARAMETER input transition times output transition times internal pull-up resistance between pin I/O and VCC output voltage (inactive)
CONDITIONS CL < = 30 pF CL < = 30 pF

TYP. 12.5 1.2 0.1

UNIT s s k
Contacts for auxiliary cards (pins C41, C81, C42 and C82); note 4 VO(inactive) cards inactive no load Iinactive = 1 mA IO(inactive) VOL VOH output current (inactive) LOW-level output voltage HIGH-level output voltage cards inactive and pin grounded I/O congured as output; IOL = 1 mA I/O congured as an output; IOH < 20 A 0 0 0.8VCC 0.1 0.0.3 VCC + 0.25 VCC + 0.25 +0.8 VCC 1.2 0.V V mA V V V V V A A s s ns k
I/O congured as an output; 0.75VCC IOH < 40 A (5 and 3 V cards) VIL VIH IIL ILIH ti(tr), ti(tf) to(tr), to(tf) tW(pu) Rint(pu) LOW-level input voltage HIGH-level output voltage LOW-level input current input leakage current HIGH input transition times output transition times width of active pull-up pulse internal pull up resistance between pins C41, C81, C42, C82 and VCC maximum frequency on pins C41, C81, C42, C82 I/O congured as an input I/O congured as an input VIL = 0 V VIH = VCC CL = 30 pF CL = 30 pF 0.3 1.5 8
f(max) Timing tact tdeact
duration of activation sequence duration of deactivation sequence

130 100

Protection and limitation ICC(sd) II/O(lim) ICLK(lim) IRST(sd) IRST(lim) Tsd shutdown and limitation current at VCC limitation current on the I/O limitation current on pin CLK shutdown current on RST limitation current on RST shutdown temperature 100 20 +10 +70 +20 mA mA mA mA mA C

SYMBOL

CONDITIONS

TYP. 10

Card presence inputs (pins PRES1, PRES2) VIL VIH IIL(L) IIL(H) VIL VIH IIL(L) IIL(H) CL VIL VIH IIL(H) IIL VOL VOH Rint(pu) ti(tr), ti(tf) to(tr), to(tf) LOW-level input voltage HIGH-level input voltage input leakage current LOW input leakage current HIGH VIN = 0 VIN = VDD 0.3VDD +10 +10 V V A A V V A A pF 0.7VDD 0.3 0.7VDD 0.3 0.7VDD 20 VIL = 0 V IOL = 1 mA IOH = 40 A 0.75VDD 8 CL = 30 pF CL = 30 pF

16 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
This data sheet contains data from the objective specication for product development. Philips Semiconductors reserves the right to change the specication in any manner without notice. This data sheet contains data from the preliminary specication. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specication without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specication. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notication (CPCN).
Preliminary data Qualication

Product data

Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status Production), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

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Koninklijke Philips Electronics N.V. 2003
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Date of release: 2003

Jul 28

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