This mode is the most powerful interrupt response mode. With a single 8-bit byte from the user, an indirect call can be made to any memory location. In this mode, the programmer maintains a table of 16-bit starting addresses for every interrupt service routine. This table may be located anywhere in memory. When an interrupt is accepted, a 16-bit pointer must be formed to obtain the desired interrupt service routine starting address from the table. The upper eight bits of this pointer is formed from the contents of the I register. The I register must be loaded with the applicable value by the programmer, such as LD I, A. A CPU reset clears the I register so that it is initialized to zero. The lower eight bits of the pointer must be supplied by the interrupting device. Only seven bits are required from the interrupting device because the least-significant bit must be a zero. This is required
because the pointer is used to get two adjacent bytes to form a complete 16bit service routine starting address and the addresses must always start in even locations.
Starting Address Pointed to by: Interrupt Service Routine Starting Address Table

Low Order High Order

I Register Contents
Seven Bits From Peripheral
Figure 16. Mode 2 Interrupt Response Mode
The first byte in the table is the least-significant (low order portion of the address). The programmer must complete this table with the correct addresses before any interrupts are accepted. The programmer can change this table by storing it in Read/Write Memory, which also allows individual peripherals to be serviced by different service routines. When the interrupting device supplies the lower portion of the pointer, the CPU automatically pushes the program counter onto the stack, obtains the starting address from the table, and performs a jump to this address. This mode of response requires 19 clock periods to complete (seven to fetch the lower eight bits from the interrupting device, six to save the program counter, and six to obtain the jump address). The Z80 peripheral devices include a daisy-chain priority interrupt structure that automatically supplies the programmed vector to the CPU during interrupt acknowledge. Refer to the Z80 CPU Peripherals User Manual for more complete information.
Hardware and Software Implementation Examples

HARDWARE Minimum System

This chapter is an introduction to implementing systems that use the Z80 CPU. Figure 17 illustrates a simple Z80 system. Any Z80 system must include the following elements:

After the execution of an instruction that sets a flag, that flag can be used to control a conditional jump or return instruction. These instructions provide logical control following the manipulation of single bit, 8-bit byte, or 18-bit data quantities. A full set of logical operations, including AND, OR, XOR (exclusive-OR), CPL (NOR), and NEG (twos complement) are available for Boolean operations between the accumulator and all other 8-bit registers, memory locations, or immediate operands. In addition, a full set of arithmetic and logical shifts in both directions are available which operate on the contents of all 8-bit primary registers or directly on any memory location. The carry flag can be included or set by these shift instructions to provide both the testing of shift results and to link register/register or register/memory shift operations.
Examples of Specific Z80 Instructions

Example One:

When a 737-byte data string in memory location DATA must be moved to location BUFFER, the operation is programmed as follows:
LD HL, DATA ;START ADDRESS OF DATA STRING LD DE, BUFFER;START ADDRESS OF TARGET BUFFER LD BC, 737 ;LENGTH OF DATA STRING LDIR ;MOVE STRING - TRANSFER MEMORY POINTED ;TO BY HL INTO MEMORY LOCATION POINTED ;TO BY DE INCREMENT HL AND DE, ;DECREMENT BC PROCESS UNTIL BC = 0.
Eleven bytes are required for this operation and each byte of data is moved in 21 clock cycles.

Example Two:

A string in memory (limited to a maximum length of 132 characters) starting at location DATA is to be moved to another memory location starting at location BUFFER until an ASCII $ (used as a string delimitor) is found. This operation is performed as follows:
HL, DATA ;STARTING ADDRESS OF DATA STRING DE, BUFFER;STARTING ADDRESS OF TARGET BUFFER BC, 132 ;MAXIMUM STRING LENGTH A, '$' ;STRING DELIMITER CODE (HL) ;COMPARE MEMORY CONTENTS WITH ;DELIMITER JR Z, END-$ ;GO TO END IF CHARACTERS EQUAL LDI ;MOVE CHARACTER (HL) to (DE) ;INCREMENT HL AND DE, DECREMENT BC JP PE, LOOP ;GO TO "LOOP" IF MORE CHARACTERS END: ;OTHERWISE, FALL THROUGH ;NOTE: P/V FLAG IS USED ;TO INDICATE THAT REGISTER BC WAS ;DECREMENTED TO ZERO. LD LD LD LD LOOP:CP
Nineteen bytes are required for this operation.

Example Three:

A 16-digit decimal number is shifted as depicted in the Figure 22. This shift is performed to mechanize BCD multiplication or division. The 16-digit decimal number is represented in packed BCD format (two BCD digits/ byte) The operation is programmed as follows:

LD HL, DATA;ADDRESS OF FIRST BYTE LD B, COUNT;SHIFT COUNT XOR A ;CLEAR ACCUMULATOR ROTAT:RLD ;ROTATE LEFT LOW ORDER DIGIT IN ACC ;WITH DIGITS IN (HL) INC HL ;ADVANCE MEMORY POINTER. DJNZ ROTAT-$ ;DECREMENT B AND GO TO ROTAT IF
;B IS NOT ZERO, OTHERWISE FALL ;THROUGH.
Eleven bytes are required for this operation.
Figure 22. Shifting of BCD Digits/Bytes

Example Four:

One number is to be subtracted from another number, both of which are in packed BCD format and are of equal but varying length. The result is stored in the location of the minuend. The operation is programmed as follows:
LD LD LD AND SUBDEC:LD SBC HL, ARG1 DE, ARG2 B, LENGTH A A, (DE) A, (HL) ;ADDRESS OF MINUEND ;ADDRESS OF SUBTRAHEND ;LENGTH OF TWO ARGUMENTS ;CLEAR CARRY FLAG ;SUBTRAHEND TO ACC ;SUBTRACT (HL) FROM ACC
DAA VALUE LD INC INC DJNZ
;ADJUST RESULT TO DECIMAL CODED (HL), A ;STORE RESULT HL ;ADVANCE MEMORY POINTERS DE SUBDEC - $;DECREMENT B AND GO TO "SUBDEC" ;IF B ;NOT ZERO, OTHERWISE FALL ;THROUGH
Seventeen bytes are required for this operation.
Examples of Programming Tasks
As depicted in Table 3, this example program sorts an array of numbers to ascending order, using a standard exchange sorting algorithm. These numbers range from 0 to 255.
Table 3. Bubble Listing Loc Obj Code Stmt Source Statement UM008005-0205 ; ; ; ; ; ; ; ; ; a b temporary storage for calculations counter for data array Hardware and Software Implementation Examples register contents use of registers at exit data sorted in ascending order ; ; ; at entry: hl contains address of data c contains number of elements to be sorted (1 <c<256) standard exchange (bubble) sort routine
Table 3. Bubble Listing (Continued) Loc Obj Code Stmt Source Statement 0007 000b 000e goof 001b 0010 001f cb05 dd2a2600 dd7edd5e3008 dd7300 dd7201 cbc4 dd23 10ea cb44 20de c42 UM008005-0205 ; Hardware and Software Implementation Examples bit jr ret flag, h nz, loop-$ ; ; ; ; ; ; ; ; sort: ld loop: res ld dec ld next: ld ld ld sub jr ld ld set noex: inc djnz (data), hl flag, h b, c b ix, (data) a, (ix) d, a e, (ix+1) e (ix), e (ix+i), d flag, h ix next-$ ; record exchange occurred ; point to next data element ; count number of comparisons ; repeat if more data pairs ; determine if exchange occurred ; continue if data unsorted ; otherwise, exit ; save data address ; initialize exchange flag ; initialize length counter ; adjust for testing ; initialize array pointer ; first element in comparison ; temporary storage for element ; second element in comparison ; comparison first to second ; exchange array elements c d e h l ix iy length of data array first element in comparison second element in comparison flag to indicate exchange unused pointer into data array unused

Three types of register indirect jumps are also included. These instructions are implemented by loading the register pair HL or one of the index registers 1X or IY directly into the PC. This feature allows for program jumps to be a function of previous calculations. A call is a special form of a jump where the address of the byte following the call instruction is pushed onto the stack before the jump is made. A return instruction is the reverse of a call because the data on the top of the stack is popped directly into the PC to form a jump address. The call and return instructions allow for simple subroutine and interrupt handling. Two special return instruction are included in the Z80 family of components. The return from interrupt instruction (RETI) and the return from nonmaskable interrupt (RETN) are treated in the CPU as an unconditional return identical to the Op Code C9H. The difference is that (RETI) can be used at the end of an interrupt routine and all Z80 peripheral chips recognize the execution of this instruction for proper control of nested priority interrupt handling. This instruction, coupled with the Z80 peripheral devices implementation, simplifies the normal return from nested interrupt. Without this feature, the following software sequence is necessary to inform the interrupting device that the interrupt routine is completed:
Disable Interrupt LD A, n OUT n, A Enable Interrupt Return Prevent interrupt before routine is exited. Notify peripheral that service routine is complete.
This seven byte sequence can be replaced with the one byte EI instruction and the two byte RETI instruction in the Z80. This is important because interrupt service time often must be minimized.
Table 15. Bit Manipulation Group
Register Addressing A Bit 8 C D E H L Reg. Indir. (HL) Indexed (IX+d) DD (IY+d) FD
Table 15. Bit Manipulation Group (Continued)
Register Addressing Test Bit 0 CCCCCCCReg. Indir. CIndexed C8 d 46 DD 1 C8 4F CCC8 4A CC8 4C C8 4D C8 4E C8 d 4E DD 2 CCCCCCCCC8 d 56 DD 3 C8 5F CCC8 5A C8 5B C8 5C C8 5D C8 5E C8 d 46 DD 4 CCCCCCCCC8 d 66 DD 5 C8 6F CCC8 6A CC8 6C C8 6D C8 6E C8 d 6E DD 6 CCCCCCCCC8 d 76 DD 7 C8 7F CCC8 7A CC8 7C CS 7D C8 7E C8 d 46 C8 d 46 FD C8 d 4E FD C8 d 56 FD C8 d 46 FD C8 d 66 FD C8 d 6E FD C8 d 76 DD C8 d 46
Register Addressing Rest Bit RES Reg. Indir. Indexed DD 0 CCCCCCCCC8 d 86 DD 1 C8 8F CCC8 8A CC8 8C C8 8D C8 8E C8 d 8E DD 2 CCCS 91 CCCCCC8 d 96 DD 3 C8 9F CCC8 9A CS 98 CCC8 9E C8 d 9E DD 4 C8 A7 C8 AO C8 AI C8 A2 C6 A3 C8 A4 C8 A5 C8 A6 C8 d A6 DD 5 C8 AF C8 A8 C8 A9 C8 AA 08 AB C8 AC C8 AD C8 AE C8 d AE DD 6 C8 B7 C8 B0 C8 B1 CC8 B3 C8 B4 C8 B5 C8 B6 C8 d B6 DD 7 C8 BF C8 B8 CC8 8A C8 B8 C8 8C C8 BD C8 9E C8 d BE FD C8 d 86 FD C8 d 8E FD C8 d 96 FD C8 d 9E FD C8 d A6 FD C8 d AE FD C8 d B6 DD C8 d BE

for extended precision arithmetic. Also, the DAA instruction sets the Carry Flag if the conditions for making the decimal adjustment are met. For instructions RLA, RRA, RLS, and RRS, the Carry bit is used as a link between the least significant byte (LSB) and most significant byte (MSB) for any register or memory location. During instructions RLCA, RLC, and SLA, the Carry contains the last value shifted out of Bit 7 of any register or memory location. During instructions RRCA, RRC, SRA, and SRL, the Carry contains the last value shifted out of Bit 0 of any register or memory location. For the logical instructions AND, OR, and XOR, the Carry is reset. The Carry Flag can also be set by the Set Carry Flag (SCF) and complemented by the Compliment Carry Flag (CCF) instructions.

Add/Subtract Flag

The Add/Subtract Flag (N) is used by the Decimal Adjust Accumulator instruction (DAA) to distinguish between ADD and SUB instructions. For ADD instructions, N is cleared to 0. For SUB instructions, N is set to 1.
The Decimal Adjust Accumulator instruction (DAA) uses this flag to distinguish between ADD and SUBTRACT instructions. For all ADD instructions, N sets to 0. For all SUBTRACT instructions, N sets to 1.
Parity/Overflow Flag (P/V)
This flag is set to a specific state depending on the operation performed. For arithmetic operations, this flag indicates an Overflow condition when the result in the Accumulator is greater than the maximum possible number
(+127) or is less than the minimum possible number (128). This Overflow condition is determined by examining the sign bits of the operands. For addition, operands with different signs never cause Overflow. When adding operands with like signs and the result has a different sign, the Overflow Flag is set, for example:
+120 +105 +225 = = = ADDEND AUGEND (-95) SUM
The two numbers added together resulted in a number that exceeds +127 and the two positive operands have resulted in a negative number (-95), which is incorrect. The Overflow Flag is therefore set. For subtraction, Overflow can occur for operands of unlike signs. Operands of like signs never cause Overflow. For example:

+127 (-) -64 +1111 MINUEND SUBTRAHEND DIFFERENCE
The minuend sign has changed from a Positive to a negative, giving an incorrect difference. Overflow is set. Another method for identifying an Overflow is to observe the Carry to and out of the sign bit. If there is a Carry in and no Carry out, or if there is no Carry in and a Carry out, then Overflow has occurred. This flag is also used with logical operations and rotate instructions to indicate the resulting parity is Even. The number of 1 bits in a byte are counted. If the total is Odd, ODD parity is flagged (P = 0). If the total is Even, EVEN parity is flagged (P = 1). During search instructions (CPI, CPIR, CPD, CPDR) and block transfer instructions (LDI, LDIR, LDD, LDDR), the P/V Flag monitors the state of the
Byte Count Register (BC). When decrementing, if the byte counter decrements to 0, the flag is cleared to 0, otherwise the flag is set to1. During LD A, I and LD A, R instructions, the P/V Flag is set with the value of the interrupt enable flip-flop (IFF2) for storage or testing. When inputting a byte from an I/O device with an IN r, (C), instruction, the P/V Flag is adjusted to indicate the data parity.

Half Carry Flag

The Half-Carry Flag (H) is set (1) or cleared (0) depending on the Carry and Borrow status between Bits 3 and 4 of an 8-bit arithmetic operation. This flag is used by the Decimal Adjust Accumulator instruction (DAA) to correct the result of a packed BCD add or subtract operation. The H Flag is set (1) or cleared (0) according to the following table:

H Flag Add Subtract

A Carry occurs from Bit 3 to Bit 4 A Borrow from Bit 4 occurs No Carry occurs from Bit 3 to Bit 4 No Borrow from Bit 4 occurs

Zero Flag

The Zero Flag (Z) is set (1) or cleared (0) if the result generated by the execution of certain instructions is 0. For 8-bit arithmetic and logical operations, the Z flag is set to a 1 if the resulting byte in the Accumulator is 0. If the byte is not 0, the Z flag is reset to 0. For compare (Search) instructions, the Z flag is set to 1 if the value in the Accumulator is equal to the value in the memory location indicated by the value of the Register pair HL. When testing a bit in a register or memory location, the Z flag contains the complemented state of the indicated bit (see Bit b, s).
When inputting or outputting a byte between a memory location and an I/O device (INI, IND, OUTI, and OUTD), if the result of decrementing the B Register is 0, the Z flag is 1, otherwise the Z flag is 0. Also for byte inputs from I/O devices using IN r, (C), the Z flag is set to indicate a 0-byte input.

Sign Flag

The Sign Flag (S) stores the state of the most-significant bit of the Accumulator (bit 7). When the Z80 performs arithmetic operations on signed numbers, the binary twos-complement notation is used to represent and process numeric information. A positive number is identified by a 0 in Bit 7. A negative number is identified by a 1. The binary equivalent of the magnitude of a positive number is stored in bits 0 to 6 for a total range of from 0 to 127. A negative number is represented by the twos complement of the equivalent positive number. The total range for negative numbers is from 1 to 128. When inputting a byte from an I/O device to a register using an IN r, (C) instruction, the S Flag indicates either positive (S = 0) or negative (S = 1) data.

Z80 Instruction Description
Execution time (E.T.) for each instruction is given in microseconds for an assumed 4 MHz clock. Total machine cycles (M) are indicated with total clock periods (T States). Also indicated are the number of T States for each M cycle. For example: M Cycles: 2T States: 7(4,3) 4 MHzE.T.: 1.75 indicates that the instruction consists of 2 machine cycles. The first cycle contains 4 clock periods (T States). The second cycle contains 3 clock periods for a total of 7 clock periods or T States. The instruction executes in 1.75 microseconds. Register format is indicated for each instruction with the most-significant bit to the left and the least-significant bit to the right.
UM008005-0205 Z80 Instruction Set

8-Bit Load Group

LD r, r'
Operation: Op Code: Operands: r, r' LD r, r'
Description: The contents of any register r' are loaded to any other register r. r, r' identifies any of the registers A, B, C, D, E, H, or L, assembled as follows in the object code: Register A B C D E H L M Cycles 1 Condition Bits Affected: None Example: If the H register contains the number 8AH, and the E register contains 10H, the instruction LD H, E results in both registers containing 10H. r, C

T States 4

MHz E.T. 1.0

LD r,n

Operation: Op Code: Operands: rn LD r, n
Description: The 8-bit integer n is loaded to any register r, where r identifies register A, B, C, D, E, H, or L, assembled as follows in the object code: Register A B C D E H L M Cycles 2 Condition Bits Affected: None Example: At execution of LD E, A5H the contents of register E are A5H. r

T States 7 (4, 3)

4 MHz E.T. 1.75

LD r, (HL)

Operation: Op Code: Operands: r (HL) LD r, (HL)
Description: The 8-bit contents of memory location (HL) are loaded to register r, where r identifies register A, B, C, D, E, H, or L, assembled as follows in the object code: Register A B C D E H L M Cycles 2 Condition Bits Affected: None Example: If register pair HL contains the number 75A1H, and memory address 75A1H contains byte 58H, the execution of LD C, (HL) results in 58H in register C. r

LD r, (IX+d)

Operation: Op Code: Operands: r (IX+d) LD r, (IX+d)

r d 0 DD

Description: The operand (IX+d), (the contents of the Index Register IX summed with a twos complement displacement integer d) is loaded to register r, where r identifies register A, B, C, D, E, H, or L, assembled as follows in the object code: Register A B C D E H L M Cycles 5 Condition Bits Affected: None Example: If the Index Register IX contains the number 25AFH, the instruction LD B, (IX+19H) causes the calculation of the sum 25AFH + 19H, which points to memory location 25C8H. If this address contains byte 39H, the instruction results in register B also containing 39H. r
T States 19 (4, 4, 3, 5, 3)

4 MHz E.T. 2.50

LD r, (IY+d)
Operation: Op Code: Operands: r (IY+D) LD r, (lY+d)

r d 0 FD

Description: The operand (lY+d) (the contents of the Index Register IY summed with a twos complement displacement integer (d) is loaded to register r, where r identifies register A, B, C, D, E, H, or L, assembled as follows in the object code: Register A B C D E H L M Cycles 5 Condition Bits Affected: None Example: If the Index Register IY contains the number 25AFH, the instruction LD B, (IY+19H) causes the calculation of the sum 25AFH + 19H, which points to memory location 25C8H. If this address contains byte 39H, the instruction results in register B also containing 39H. r

4 MHz E.T. 4.75

LD (HL), r
Operation: Op Code: Operands: (HL) r LD (HL), r
Description: The contents of register r are loaded to the memory location specified by the contents of the HL register pair. The symbol r identifies register A, B, C, D, E, H, or L, assembled as follows in the object code: Register A B C D E H L M Cycles 2 Condition Bits Affected: None Example: If the contents of register pair HL specifies memory location 2146H, and the B register contains byte 29H, at execution of LD (HL), B memory address 2146H also contains 29H. r

LD (IX+d), r

Operation: Op Code: Operands: (IX+d) r LD (IX+d), r

d r 1 DD

Description: The contents of register r are loaded to the memory address specified by the contents of Index Register IX summed with d, a twos complement displacement integer. The symbol r identifies register A, B, C, D, E, H, or L, assembled as follows in the object code: Register A B C D E H L M Cycles 5 Condition Bits Affected: None Example: If the C register contains byte 1CH, and the Index Register IX contains 3100H, then the instruction LID (IX+6H), C performs the sum 3100H + 6H and loads 1CH to memory location 3106H. r

LD (IY+d), r

Operation: Op Code: Operands: (lY+d) r LD (lY+d), r

d r 1 FD

Description: The contents of resister r are loaded to the memory address specified by the sum of the contents of the Index Register IY and d, a twos complement displacement integer. The symbol r is specified according to the following table. Register A B C D E H L M Cycles 5 Condition Bits Affected: None Example: If the C register contains byte 48H, and the Index Register IY contains 2A11H, then the instruction LD (IY+4H), C performs the sum 2A11H + 4H, and loads 48H to memory location 2A15. r

LD (HL), n

Operation: Op Code: Operands: (HL) n LD (HL), n
Description: Integer n is loaded to the memory address specified by the contents of the HL register pair. M Cycles 3 Condition Bits Affected: None Example: If the HL register pair contains 4444H, the instruction LD (HL), 28H results in the memory location 4444H containing byte 28H. T States 10 (4, 3, 3) 4 MHz E.T. 2.50

LD (IX+d), n

Operation: Op Code: Operands: (IX+d) n LD (IX+d), n

d n DD 36

Description: The n operand is loaded to the memory address specified by the sum of the Index Register IX and the twos complement displacement operand d. M Cycles 5 Condition Bits Affected: None Example: If the Index Register IX contains the number 219AH, the instruction LD (IX+5H), 5AH results in byte 5AH in the memory address 219FH. T States 19 (4, 4, 3,5,3) 4 MHz E.T. 4.75

LD (IY+d), n

Operation: Op Code: Operands: (lY+d) n LD (lY+d), n

d n FD 36

Description: Integer n is loaded to the memory location specified by the contents of the Index Register summed with the twos complement displacement integer d. M Cycles 5 Condition Bits Affected: None Example: If the Index Register IY contains the number A940H, the instruction LD (IY+10H), 97H results in byte 97H in memory location A950H. T States 19 (4, 4, 3, 5, 3) 4 MHz E.T. 2.50

LD A, (BC)

Operation: Op Code: Operands: A (BC) LD A, (BC)
Description: The contents of the memory location specified by the contents of the BC register pair are loaded to the Accumulator. M Cycles 2 Condition Bits Affected: None Example: If the BC register pair contains the number 4747H, and memory address 4747H contains byte 12H, then the instruction LD A, (BC) results in byte 12H in register A. T States 7 (4, 3) 4 MHz E.T. 1.75

LD A, (DE)

Operation: Op Code: Operands: A (DE) LD A, (DE)
Description: The contents of the memory location specified by the register pair DE are loaded to the Accumulator. M Cycles 2 Condition Bits Affected: None Example: If the DE register pair contains the number 30A2H and memory address 30A2H contains byte 22H, then the instruction LD A, (DE) results in byte 22H in register A. T States 7 (4, 3) 4 MHz E.T. 1.75

LD A, (nn)

Operation: Op Code: Operands: A (nn) LD A, (nn)

at execution of RLCA the contents of the Accumulator and Carry flag are

7 A 0 CY

Description: The contents of the Accumulator (register A) are rotated left 1-bit position through the Carry flag. The previous content of the Carry flag is copied to bit 0. Bit 0 is the least-significant bit. M Cycles 1 T States MHz E.T. 1.00
Condition Bits Affected: Condition Bits Affected S is not affected Z is not affected H is reset P/V is not affected N is reset C is data from bit 7 of Accumulator Example: If the contents of the Accumulator and the Carry flag are
at execution of RLA the contents of the Accumulator and the Carry flag are
Description: The contents of the Accumulator (register A) are rotated right 1-bit position. Bit 0 is copied to the Carry flag and also to bit 7. Bit 0 is the leastsignificant bit. M Cycles 1 Condition Bits Affected: S is not affected Z is not affected H is reset P/V is not affected N is reset C is data from bit 0 of Accumulator Example: If the contents of the Accumulator are
at execution of RRCA the contents of the Accumulator and the Carry flag are
Description: The contents of the Accumulator (register A) are rotated right 1-bit position through the Carry flag. The previous content of the Carry flag is copied to bit 7. Bit 0 is the least-significant bit. M Cycles 1 Condition Bits Affected: S is not affected Z is not affected H is reset P/V is not affected N is reset C is data from bit 0 of Accumulator Example: If the contents of the Accumulator and the Carry Flag are
at execution of RRA the contents of the Accumulator and the Carry flag are

CY 7 r 0

r 1 CB
Description: The contents of register r are rotated left 1-bit position. The content of bit 7 is copied to the Carry flag and also to bit 0. Operand r is specified as follows in the assembled object code: Register B C D E H L A M Cycles 2 Condition Bits Affected: S is set if result is negative; reset otherwise Z is set if result is zero; reset otherwise H is reset P/V is set if parity even; reset otherwise N is reset C is data from bit 7 of source register
If the contents of register r are
at execution of RLC r the contents of register r and the Carry flag are

Description: The contents of operand m are rotated right 1-bit position through the Carry flag. The content of bit 0 is copied to the Carry flag and the previous content of the Carry flag is copied to bit 7. Bit 0 is the least-significant bit. Instruction RR r RR (HL) RR (IX+d) RR (lY+d) Condition Bits Affected: S is set if result is negative; reset otherwise Z is set if result is zero; reset otherwise H is reset P/V is set if parity even; reset otherwise, N is reset C is data from bit 0 of source register Example: If the contents of the HL register pair are 4343H, and the contents of memory location 4343H and the Carry flag are
M Cycles T States (4, 4) (4, 4, 4, 3) (4, 4, 3, 5, 4, 3) (4, 4, 3, 5, 4, 3)
at execution of RR (HL) the contents of location 4343H and the Carry flag are

CY 7 m 0 0

SLA m The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous RLC instructions. These possible Op Code/operand combinations are specified as follows in the assembled object code

SLA r*

SLA (HL)

CB 26 DD CB

SLA (IX+d)

0 SLA (IY+d) 1 1

26 FD CB
Description: An arithmetic shift left 1-bit position is performed on the contents of operand m. The content of bit 7 is copied to the Carry flag. Bit 0 is the least-significant bit. Instruction SLA r SLA (HL) SLA (IX+d) SLA (IY+d) Condition Bits Affected: S is set if result is negative; reset otherwise Z is set if result is zero; reset otherwise H is reset P/V is set if parity is even; reset otherwise N is reset C is data from bit 7 Example: If the contents of register L are
at execution of SLA L the contents of register L and the Carry flag are
SRA m The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous PLC instructions. These possible Op Code/operand combinations are specified as follows in the assembled object code:
SRA r* SRA (HL) SRA (IX+d) d 0 SRA (IY+d) 0 d 2E 2E FD CB r* CB 2E DD CB 1 CB
Description: An arithmetic shift right 1-bit position is performed on the contents of operand m. The content of bit 0 is copied to the Carry flag and the previous content of bit 7 is unchanged. Bit 0 is the least-significant bit. Instruction SRA r SRA (HL) SRA (IX+d) SRA (lY+d) Condition Bits Affected: S is set if result is negative; reset otherwise Z is set if result is zero; reset otherwise H is reset P/V is set if parity is even; reset otherwise N is reset C is data from bit 0 of source register Example: If the contents of the Index Register IX are 1000H, and the contents of memory location 1003H are

at execution of RRD the contents of the Accumulator and memory location

5000H are

Bit Set, Reset, and Test Group

BIT b, r

Operation: Op Code: Operands: Z rb BIT b, r

b 1 r 1 CB

Description: This instruction tests bit b in register r and sets the Z flag accordingly. Operands b and r are specified as follows in the assembled object code: Bit Tested M Cycles 2 b

110 111

Register B C D E H L A 4 MHz E.T. 4.50
Condition Bits Affected: S is unknown Z is set if specified bit is 0; reset otherwise H is set P/V is unknown N is reset C is not affected Example: If bit 2 in register B contains 0, at execution of BIT 2, B the Z flag in the F register contains 1, and bit 2 in register B remains 0. Bit 0 in register B is the least-significant bit.

BIT b, (HL)

Operation: Op Code: Operands: Z (HL)b BIT b, (HL)

b 0 CB

Description: This instruction tests bit b in the memory location specified by the contents of the HL register pair and sets the Z flag accordingly. Operand b is specified as follows in the assembled object code: Bit Tested M Cycles 3 Condition Bits Affected: S is unknown Z is set if specified Bit is 0; reset otherwise H is set P/V is unknown H is reset C is not affected b

T States 12 (4, 4, 4) 4

4 MHz E.T. 3.00
If the HL register pair contains 4444H, and bit 4 in the memory location 444H contains 1, at execution of BIT 4, (HL) the Z flag in the F register contains 0, and bit 4 in memory location 4444H still contains 1. Bit 0 in memory location 4444H is the least-significant bit.

BIT b, (IX+d)

Operation: Op Code: Operands: Z (IX+d)b BIT b, (IX+d)

d b 1 DD CB

Description: This instruction tests bit b in the memory location specified by the contents of register pair IX combined with the twos complement displacement d and sets the Z flag accordingly. Operand b is specified as follows in the assembled object code. Bit Tested M cycles 5 b
T States 20 (4, 4, 3, 5, 4)

4 MHz E.T. 5.00

Condition Bits Affected: S is unknown Z is set if specified Bit is 0; reset otherwise H is set P/V is unknown N is reset C is not affected Example: If the contents of Index Register IX are 2000H, and bit 6 in memory location 2004H contains 1, at execution of BIT 6, (IX+4H) the Z flag in the F register contains 0, and bit 6 in memory location 2004H still contains 1. Bit 0 in memory location 2004H is the least-significant bit.

Condition Bits Affected: S is unknown Z is set H is unknown P/V is unknown N is set C is not affected Example: If the contents of register C are 07H, the contents of register B are 03H, the contents of the HL register pair are 1000H, and memory locations have the following contents: contains 51H contains A9H contains 03H then at execution of OTDR the HL register pair contain 0FFDH, register B contains zero, and a group of bytes is written to the peripheral device mapped to I/O port address 07H in the following sequence:
0FFEH 0FFFH 1000H 03H A9H 51H

Z8400/84C00

NMOS/CMOS Z80 CPU CENTRAL PROCESSING UNIT

FEATURES

The Extensive Instruction Set.Contains 158 Instructions, Including the 8080A Instructions Set as a Subset. Single 5 Volt Power Supply NMOS Version for Low Cost, High Performance Solutions; CMOS Version for High Performance, Low Power Designs. NMOS Z084004 - 4 MHz Z0840006 - 6.17 MHz Z084008 - 8 MHz CMOS Z0840006 - DC to 6.17 MHz Z84C0008 - DC to 8 MHz Z84C0010 - DC to 10 MHz Z84C0020 - DC to 20 MHz 6 MHz Version can be Operated at 6.144 MHz Clock Speed
The Z80 Microprocessors and Associated Family of Peripherals can be Linked by a Vectored Interrupt System. This System can be Daisy-Chained to Allow Implementation of a Priority Interrupt Scheme. Duplicate Set of Both General-Purpose and Flag Registers Two 16-Bit Index Registers Three Modes of Maskable Interrupts: - Mode 0 - 8080A Similar - Mode 1 - Non-Z80 Environment, Location 38H - Mode 2 - Z80 Family Peripherals, Vectored Interrupts On-Chip Dynamic Memory Refresh Counter

GENERAL DESCRIPTION

The Z8400/Z84C00 CPUs are fourth-generation enhanced microprocessors with exceptional computational power. They offer higher system throughput and more efficient memory utilization than comparable second- and thirdgeneration microprocessors. The speed offerings from MHz suit a wide range of applications which migrate software. The internal registers contain 208 bits of read/ write memory that are accessible to the programmer. These registers include two sets of six general purpose registers which may be used individually as either 8-bit registers or as 16-bit register pairs. In addition, there are two sets of accumulator and flag registers. A group of Exchange instructions makes either set of main or alternate registers accessible to the programmer. The alternate set allows operation in foreground-background mode or it may be reserved for very fast interrupt response. The CPU also contains a Stack Pointer, Program Counter, two index registers, a Refresh register (counter), and an Interrupt register. The CPU is easy to incorporate into a system since it requires only a single +5V power source. All output signals are fully decoded and timed to control standard memory or peripheral circuits; the CPU is supported by an extensive family of peripheral controllers.

PB006301-0301

GENERAL DESCRIPTION (Continued)

8-Bit Data Bus

Data Bus Interface
Instruction Decoder +5V GND Clock CPU Timing Control

Instruction Register

Internal Data Bus
Register Array CPU Timing
8 Systems and CPU Control Outputs

5 CPU Control Inputs

Address Logic and Buffers

16-Bit Address Bus

Figure 1. Z8400/C00 Functional Block Diagram
1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.

Zilogs products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 Telex 910-338-7621 FAX 408 370-8056 Internet: http://www.zilog.com