Manual Objectives

This user manual describes the architecture and instruction set of the Z80 CPU.

About This Manual

ZiLOG recommends that the user read and understand everything in this manual before setting up and using the product. However, we recognize that users have different styles of learning: some will want to set up and use their new evaluation kit while they read about it; others will open these pages only to check on a particular specification. Therefore, we have designed this manual to be used either as a how to procedural manual or a reference guide to important data.

Intended Audience

This document is written for ZiLOG customers who are experienced at working with microprocessors or in writing assembly code or compilers.

Manual Organization

The Z80 CPU Users Manual is divided into four chapters. Overview Presents an overview of the Users Manual Architecture, Pin descriptions, timing and Interrupt Response. Hardware and Software Implementation Presents examples of the Users Manual hardware and software.

Users Manual Z80 CPU xx

Z80 CPU Instruction Description Presents the Users Manual instruction types, addressing modes and instruction Op Codes. Z80 Instruction Set Presents an overview of the Users Manual assenbly language, status indicator flags and the Z80 instructions. Related Documents
Part Number Part Number Part Number Title Title Title DC number DC number DC number

Manual Conventions

The following assumptions and conventions are adopted to provide clarity and ease of use: Use of the Words Set and Clear The words set and clear imply that a register bit or a condition contains the values logical 1 and logical 0, respectively. When either of these terms is followed by a number, the word logical may not be included, but it is implied. Notation for Bits and Similar Registers A field of bits within a register is designated as: Register (nn). For example: PWM_CR (3120). A field of bits within a bus is designated as: Busnn. For example: PCntl74. A range of similar (whole) registers is designated as: RegisternRegistern. For example: OPBCS5OPBCS0.
Use of the Terms LSB and MSB In this document, the terms LSB and MSB, when appearing in upper case, mean least significant byte and most significant byte, respectively. The lowercase forms, msb and lsb, mean least significant bit and most significant bit, respectively. Courier Font Commands, code lines and fragments, register (and other) mnemonics, values, equations, and various executable items are distinguished from general text by the use of the Courier font. This convention is not used within tables. For example: The STP bit in the CNTR register must be 1. Where the use of the font is not possible, as in the Index, the name of the entity is presented in upper case. Hexadecimal Values Designated by H Hexadecimal values are designated by a uppercase H and appear in the Courier typeface. For example: STAT is set to F8H. Use of All Uppercase Letters The use of all uppercase letters designates the names of states and commands. For example: The receiver can force the SCL line to Low to force the transmitter into a WAIT state. The bus is considered BUSY after the Start condition. A START command triggers the processing of the initialization sequence. Use of Initial Uppercase Letters Initial uppercase letters designate settings, modes, and conditions in general text. For example: The Slave receiver leaves the data line High. In Transmit mode, the byte is sent most significant bit first. The Master can generate a Stop condition to abort the transfer.

Users Manual Z80 CPU xxii
Register Access Abbreviations Register access is designated by the following abbreviations:
Designation R R/W W Description Read Only Read/Write Write Only Unspecified or indeterminate

Trademarks

Z80, Z180, Z380 and Z80382 are trademarks of ZiLOG, Inc.

Overview

ARCHITECTURE
The ZiLOG Z80 CPU family of components are fourth-generation enhanced microprocessors with exceptional computational power. They offer higher system throughput and more efficient memory utilization than comparable second- and third-generation microprocessors. The speed offerings from MHz suit a wide range of applications which migrate software. The internal registers contain 208 bits of read/write memory that are accessible to the programmer. These registers include two sets of six general purpose registers which may be used individually as either 8-bit registers or as 16-bit register pairs. In addition, there are two sets of accumulator and flag registers. The Z80 CPU also contains a Stack Pointer, Program Counter, two index registers, a REFRESH register, and an INTERRUPT register. The CPU is easy to incorporate into a system since it requires only a single +5V power source. All output signals are fully decoded and timed to control standard memory or peripheral circuits; the Z80 CPU is supported by an extensive family of peripheral controllers. Figure 1 illustrates the internal architecture and major elements of the Z80 CPU.

Data Bus Control

I 13 CPU and System Control Signals n

Inst. Register

Internal Data Bus

CPU Control

CPU Registers

Address Control

+5V GND CLK

16-Bit Address Bus

Figure 1.

Z80 CPU Block Diagram

The Z80 CPU contains 208 bits of R/W memory that are available to the programmer. Figure 2 illustrates how this memory is configured to eighteen 8-bit registers and four 16-bit registers. All Z80 registers are implemented using static RAM. The registers include two sets of six general-purpose registers that may be used individually as 8-bit registers or in pairs as 16-bit registers. There are also two sets of accumulator and flag registers and six special-purpose registers.
Main Register Set Accumulator A B D H Interrupt Vector I Index Register Index Register Stack Pointer Program Counter Flags F C E L

the 8-bit Op Code. This is possible because only eight separate addresses located in page zero of the external memory may be specified. Program jumps may also be achieved by loading register HL, IX, or IY directly into the PC, thus allowing the jump address to be a complex function of the routine being executed. The input/output group of instructions in the Z80 allow for a wide range of transfers between external memory locations or the general-purpose CPU registers, and the external I/O devices. In each case, the port number is provided on the lower eight bits of the address bus during any I/O transaction. One instruction allows this port number to be specified by the second byte of the instruction while other Z80 instructions allow it to be specified as the content of the C register. One major advantage of using the C register as a pointer to the I/O device is that it allows multiple I/O ports to share common software driver routines. This advantage is not possible when the address is part of the Op Code if the routines are stored in ROM. Another feature of these input instructions is the automatic setting of the flag register, making additional operations unnecessary to determine the state of the input data. The parity state is one example. The Z80 CPU includes single instructions that can move blocks of data (up to 256 bytes) automatically to or from any I/O port directly to any memory location. In conjunction with the dual set of general-purpose registers, these instructions provide fast I/O block transfer rates. The power of this I/O instruction set is demonstrated by the Z80 CPU providing all required floppy disk formatting on double-density floppy disk drives on an interrupt-driven basis. For example, the CPU provides the preamble, address, data, and enables the CRC codes. Finally, the basic CPU control instructions allow various options and modes. This group includes instructions such as setting or resetting the interrupt enable flip-flop or setting the mode of interrupt response.

Addressing Modes

Most of the Z80 instructions operate on data stored in internal CPU registers, external memory, or in the I/O ports. Addressing refers to how the address of this data is generated in each instruction. This section is a brief summary of the types of addressing used in the Z80 while subsequent sections detail the type of addressing available for each instruction group. Immediate In this mode of addressing, the byte following the Op Code in memory contains the actual operand.

Address

N, N+1 N+2 to N+9 N+10,N+11 N + 12

Instruction

LD B, 7 (Perform a sequence of instructions) DJNZ -8 (Next Instruction)

Comments

: set B register to count of 7 : loop to be performed 7 times : to jump from N+12 to N+2
Table 17 lists the eight Op Codes for the restart instruction. This instruction is a single byte call to any of the eight addresses listed. The simple mnemonic for these eight calls is also listed. This instruction is useful for frequently-used routines because memory consumption is minimized.
Table 17. Restart Group Op Code
CALL Address 0000H 0008H 0010H 0018H 0020H 0028H 0030H 0038H C7 CF D7 DF E7 EF F7 FF RST 0 RST 8 RST 16 RST 24 RST 32 RST 40 RST 48 RST 56

Input/Output

The Z80 has an extensive set of input and output instructions as shown in Table 18 and Table 19. The addressing of the input or output device can be either absolute or register indirect, using the C register. In the register indirect addressing mode, data can be transferred between the I/O devices and any of the internal registers. In addition, eight block transfer instructions have been implemented. These instructions are similar to the memory block transfers except that they use register pair HL for a pointer to the memory source (output commands) or destination (input commands) while register B is used as a byte counter. Register C holds the address of the port for which the input or output command is required. Because register B is eight bits in length, the I/O block transfer command handles up to 256 bytes. In the instructions IN A, and OUT n, A, the I/O device address n appears in the lower half of the address bus (A7-A0) while the accumulator content
is transferred in the upper half of the address bus. In all register indirect input output instructions, including block I/O transfers, the content of register C is transferred to the lower half of the address bus (device address) while the content of register B is transferred to the upper half of the address bus.

Byte Count Register (BC). When decrementing, if the byte counter decrements to 0, the flag is cleared to 0, otherwise the flag is set to1. During LD A, I and LD A, R instructions, the P/V Flag is set with the value of the interrupt enable flip-flop (IFF2) for storage or testing. When inputting a byte from an I/O device with an IN r, (C), instruction, the P/V Flag is adjusted to indicate the data parity.

Half Carry Flag

The Half-Carry Flag (H) is set (1) or cleared (0) depending on the Carry and Borrow status between Bits 3 and 4 of an 8-bit arithmetic operation. This flag is used by the Decimal Adjust Accumulator instruction (DAA) to correct the result of a packed BCD add or subtract operation. The H Flag is set (1) or cleared (0) according to the following table:

H Flag Add Subtract

A Carry occurs from Bit 3 to Bit 4 A Borrow from Bit 4 occurs No Carry occurs from Bit 3 to Bit 4 No Borrow from Bit 4 occurs

Zero Flag

The Zero Flag (Z) is set (1) or cleared (0) if the result generated by the execution of certain instructions is 0. For 8-bit arithmetic and logical operations, the Z flag is set to a 1 if the resulting byte in the Accumulator is 0. If the byte is not 0, the Z flag is reset to 0. For compare (Search) instructions, the Z flag is set to 1 if the value in the Accumulator is equal to the value in the memory location indicated by the value of the Register pair HL. When testing a bit in a register or memory location, the Z flag contains the complemented state of the indicated bit (see Bit b, s).
When inputting or outputting a byte between a memory location and an I/O device (INI, IND, OUTI, and OUTD), if the result of decrementing the B Register is 0, the Z flag is 1, otherwise the Z flag is 0. Also for byte inputs from I/O devices using IN r, (C), the Z flag is set to indicate a 0-byte input.

Sign Flag

The Sign Flag (S) stores the state of the most-significant bit of the Accumulator (bit 7). When the Z80 performs arithmetic operations on signed numbers, the binary twos-complement notation is used to represent and process numeric information. A positive number is identified by a 0 in Bit 7. A negative number is identified by a 1. The binary equivalent of the magnitude of a positive number is stored in bits 0 to 6 for a total range of from 0 to 127. A negative number is represented by the twos complement of the equivalent positive number. The total range for negative numbers is from 1 to 128. When inputting a byte from an I/O device to a register using an IN r, (C) instruction, the S Flag indicates either positive (S = 0) or negative (S = 1) data.

Z80 Instruction Description
Execution time (E.T.) for each instruction is given in microseconds for an assumed 4 MHz clock. Total machine cycles (M) are indicated with total clock periods (T States). Also indicated are the number of T States for each M cycle. For example: M Cycles: 2T States: 7(4,3) 4 MHzE.T.: 1.75 indicates that the instruction consists of 2 machine cycles. The first cycle contains 4 clock periods (T States). The second cycle contains 3 clock periods for a total of 7 clock periods or T States. The instruction executes in 1.75 microseconds. Register format is indicated for each instruction with the most-significant bit to the left and the least-significant bit to the right.
UM008005-0205 Z80 Instruction Set

8-Bit Load Group

LD r, r'
Operation: Op Code: Operands: r, r' LD r, r'
Description: The contents of any register r' are loaded to any other register r. r, r' identifies any of the registers A, B, C, D, E, H, or L, assembled as follows in the object code: Register A B C D E H L M Cycles 1 Condition Bits Affected: None Example: If the H register contains the number 8AH, and the E register contains 10H, the instruction LD H, E results in both registers containing 10H. r, C

T States 4

MHz E.T. 1.0

LD r,n

Operation: Op Code: Operands: rn LD r, n
Description: The 8-bit integer n is loaded to any register r, where r identifies register A, B, C, D, E, H, or L, assembled as follows in the object code: Register A B C D E H L M Cycles 2 Condition Bits Affected: None Example: At execution of LD E, A5H the contents of register E are A5H. r

T States 7 (4, 3)

4 MHz E.T. 1.75

LD r, (HL)

Operation: Op Code: Operands: r (HL) LD r, (HL)
Description: The 8-bit contents of memory location (HL) are loaded to register r, where r identifies register A, B, C, D, E, H, or L, assembled as follows in the object code: Register A B C D E H L M Cycles 2 Condition Bits Affected: None Example: If register pair HL contains the number 75A1H, and memory address 75A1H contains byte 58H, the execution of LD C, (HL) results in 58H in register C. r

LD r, (IX+d)

Operation: Op Code: Operands: r (IX+d) LD r, (IX+d)

r d 0 DD

Description: The operand (IX+d), (the contents of the Index Register IX summed with a twos complement displacement integer d) is loaded to register r, where r identifies register A, B, C, D, E, H, or L, assembled as follows in the object code: Register A B C D E H L M Cycles 5 Condition Bits Affected: None Example: If the Index Register IX contains the number 25AFH, the instruction LD B, (IX+19H) causes the calculation of the sum 25AFH + 19H, which points to memory location 25C8H. If this address contains byte 39H, the instruction results in register B also containing 39H. r

EX AF, AF'

Operation: Op Code: Operands: AF AF' EX AF, AF'
Description: The 2-byte contents of the register pairs AF and AF are exchanged. Register pair AF consists of registers A' and F'. M Cycles 1 Condition Bits Affected: None Example: If the content of register pair AF is number 9900H, and the content of register pair AF is number 5944H, at instruction EX AF, AF' the contents of AF is 5944H, and the contents of AF' is 9900H. T States MHz E.T. 1.00
Operation: Op Code: Operands: (BC) (BC'), (DE) (DE'), (HL) (HL') EXX
Description: Each 2-byte value in register pairs BC, DE, and HL is exchanged with the 2-byte value in BC', DE', and HL', respectively. M Cycles 1 Condition Bits Affected: None Example: If the contents of register pairs BC, DE, and HL are the numbers 445AH, 3DA2H, and 8859H, respectively, and the contents of register pairs BC', DE', and HL' are 0988H, 9300H, and 00E7H, respectively, at instruction EXX the contents of the register pairs are as follows: BC' contains 0988H; DE' contains 9300H; HL contains 00E7H; BC' contains 445AH; DE' contains 3DA2H; and HL' contains 8859H. T States MHz E.T. 1.00

EX (SP), HL

Operation: Op Code: Operands: H (SP+1), L (SP) EX (SP), HL
Description: The low order byte contained in register pair HL is exchanged with the contents of the memory address specified by the contents of register pair SP (Stack Pointer), and the high order byte of HL is exchanged with the next highest memory address (SP+1). M Cycles 5 Condition Bits Affected: None Example: If the HL register pair contains 7012H, the SP register pair contains 8856H, the memory location 8856H contains byte 11H, and memory location 8857H contains byte 22H, then the instruction EX (SP), HL results in the HL register pair containing number 2211H, memory location 8856H containing byte 12H, memory location 8857H containing byte 70H and Stack Pointer containing 8856H. T States 19 (4, 3, 4, 3, 5) 4 MHz E.T. 4.75

EX (SP), IX

Operation: Op Code: Operands: IXH (SP+1), IXL (SP) EX (SP), IX
Description: The low order byte in Index Register IX is exchanged with the contents of the memory address specified by the contents of register pair SP (Stack Pointer), and the high order byte of IX is exchanged with the next highest memory address (SP+1). M cycles 6 Condition Bits Affected: None Example: If the Index Register IX contains 3988H, the SP register pair Contains 0100H, memory location 0100H contains byte 90H, and memory location 0101H contains byte 48H, then the instruction EX (SP), IX results in the IX register pair containing number 4890H, memory location 0100H containing 88H, memory location 0101H containing 39H, and the Stack Pointer containing 0100H. T States 23 (4, 4, 3, 4, 3, 5) 4 MHz E.T. 5.75

ADD A, (IY + d)

Operation: Op Code: Operands: A A + (ID+d) ADD A, (IY + d)

d FD 86

Description: The contents of the Index Register (register pair IY) is added to a twos complement displacement d to point to an address in memory. The contents of this address is then added to the contents of the Accumulator, and the result is stored in the Accumulator. M Cycles 5 Condition Bits Affected: S is set if result is negative; reset otherwise Z is set if result is zero; reset otherwise H is set if carry from bit 3: reset otherwise P/V is set if overflow; reset otherwise N is reset C is set if carry from bit 7; reset otherwise Example: If the Accumulator contents are 11H, the Index Register Pair IY contains 1000H, and if the content of memory location 1005H is 22H, at execution of ADD A, (IY + 5H) the contents of the Accumulator are 33H. T States 19(4, 4, 3, 5, 3) 4 MHz E.T. 4.75

ADC A, s

Operation: Op Code: Operands: A A + s + CY ADC A, s This s operand is any of r, n, (HL), (IX+d), or (lY+d) as defined for the analogous ADD instruction. These possible Op Code/operand combinations are assembled as follows in the object code:
ADC A,r ADC A,n n ADC A, (HL) ADC A, (IX+d) d ADC A, (IY+d) d FD 8E 8E DD 8E 1 r* CE
*r identifies registers B, C, D, E, H, L, or A assembled as follows in the object code field above:

Register B C D E H L A

Description: The s operand, along with the Carry Flag (C in the F register) is added to the contents of the Accumulator, and the result is stored in the Accumulator. Instruction M Cycle ADC A, r 1 ADC A, n 2 ADC A, (HL) 2 ADC A, (IX+d) 5 ADC A, (lY+d) 5 Condition Bits Affected: S is set if result is negative; reset otherwise Z is set if result is zero; reset otherwise H is set if carry from bit 3; reset otherwise P/V is set if overflow; reset otherwise N is reset C is set if carry from bit 7: reset otherwise Example: If the Accumulator contents are 16H, the Carry Flag is set, the HL register pair contains 6666H, and address 6666H contains 10H, at execution of ADC A, (HL) the Accumulator contains 27H. T States (4, 3) 7 (4, 3) 19 (4, 4, 3, 5, 3) 19 (4, 4, 3, 5, 3) 4 MHz E.T. 1.00 1.75 1.75 4.75 4.75
Operation: Op Code: Operands: AA-s SUB s This s operand is any of r, n, (HL), (IX+d), or (lY+d) as defined for the analogous ADD instruction. These possible Op Code/operand combinations are assembled as follows in the object code:
SUB r SUB n n SUB (HL) SUB (IX+d) d SUB (IY+d) d FD DD r* D6
Description: The s operand is subtracted from the contents of the Accumulator, and the result is stored in the Accumulator. Instruction SUB r SUB n SUB (HL) SUB (IX+d) SUB (lY+d) Condition Bits Affected: S is set if result is negative; reset otherwise Z is set if result is zero; reset otherwise H is set if borrow from bit 4; reset otherwise P/V is set if overflow; reset otherwise N is set C is set if borrow; reset otherwise Example: If the Accumulator contents are 29H, and register D contains 11H, at execution of SUB D the Accumulator contains 18H. M Cycle 5 T States (4, 3) 7 (4, 3) 19 (4, 4, 3, 5, 3) 19 (4, 4, 3, 5, 3) 4 MHz E.T. 1.00 1.75 1.75 4.75 4.75

Description: A logical OR operation is performed between the byte specified by the s operand and the byte contained in the Accumulator; the result is stored in the Accumulator. Instruction OR r OR n OR (HL) OR (IX+d) OR (lY+d) Condition Bits Affected: S is set if result is negative; reset otherwise Z is set if result is zero; reset otherwise H is reset P/V is set if overflow; reset otherwise N is reset C is reset Example: If the H register contains 48H (0100 0100), and the Accumulator contains 12H (0001 0010), at execution of OR H the Accumulator contains 5AH (0101 1010). M cycles 5 T States (4, 3) 7 (4, 3) 19 (4, 4, 3, 5, 3) 19 (4, 4, 3, 5, 3) 4 MHz E.T. 1.00 1.75 1.75 4.75 4.75
Operation: Op Code: Operands: AA s XOR s The s operand is any of r, n, (HL), (IX+d), or (lY+d), as defined for the analogous ADD instructions. These possible Op Code/operand combinations are assembled as follows in the object code:
Description: The logical exclusive-OR operation is performed between the byte specified by the s operand and the byte contained in the Accumulator; the result is stored in the Accumulator. Instruction XOR r XOR n XOR (HL) XOR (IX+d) XOR (lY+d) Condition Bits Affected: S is set if result is negative; reset otherwise Z is set if result is zero; reset otherwise H is reset P/V is set if parity even; reset otherwise N is reset C is reset Example: If the Accumulator contains 96H (1001 0110), at execution of XOR 5DH (5DH = 0101 1101) the Accumulator contains CBH (1100 1011). M Cycles 5 T States 4 MHz E.T. 4 1.(4, 3) 1.(4, 3) 1.(4, 4, 3, 5, 3) 4.(4, 4, 3, 5, 3) 4.75
Operation: Op Code: Operands: A-s CP s The s operand is any of r, n, (HL), (IX+d), or (lY+d), as defined for the analogous ADD instructions. These possible Op Code/operand combinations are assembled as follows in the object code:
CP r* CP n n CP (HL) CP (IX+d) d CP (IY+d) d FD BE BE DD BE 1 r* FE
Description: The contents of the s operand are compared with the contents of the Accumulator. If there is a true compare, the Z flag is set. The execution of this instruction does not affect the contents of the Accumulator. Instruction CP r CP n CP (HL) CP (IX+d) CP (lY+d) Condition Bits Affected: S is set if result is negative; reset otherwise Z is set if result is zero; reset otherwise H is set if borrow from bit 4; reset otherwise P/V is set if overflow; reset otherwise N is set C is set if borrow; reset otherwise Example: If the Accumulator contains 63H, the HL register pair contains 6000H, and memory location 6000H contains 60H, the instruction CP (HL) results in the PN flag in the F register resetting. M Cycles T States 2 7(4, 3) (4, 3) (4, 4, 3, 5, 3) (4, 4, 3, 5, 3) 4 MHz E.T. 1.00 1.75 1.75 4.75 4.75

M Cycles T States (4, 4) 4 15(4, 4, 4, 3) (4, 4, 3, 5, 4, 3) (4, 4, 3, 5, 4, 3)
4 MHz E.T. 2.00 3.75 5.75 5.75
at execution of RL D the contents of register D and the Carry flag are

7 m 0 CY

RRC m The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous RLC instructions. These possible Op Code/operand combinations are specified as follows in the assembled object code:
RRC r* RRC (HL) RRC (IX+d) d 0 RRC (IY+d) 0 d OE OE FB CB r* CB OE DD CB 1 CB
Description: The contents of the m operand are rotated right 1-bit position. The content of bit 0 is copied to the Carry flag and also to bit 7. Bit 0 is the leastsignificant bit. Instruction RRC r RRC (HL) RRC (IX+d) RRC (lY+d) Condition Bits Affected: S is set if result is negative; reset otherwise Z is set if result is zero; reset otherwise H is reset P/V is set if parity even; reset otherwise, N is reset C is data from bit 0 of source register Example: If the contents of register A are

M cycles 6 6

T States 4 MHz E.T. 8 (4, 4) 2.(4, 4, 4, 3) 3.(4, 4, 3, 5, 4, 3) 5.(4, 4, 3, 5, 4, 3) 5.75
at execution of RRC A the contents of register A and the Carry flag are
RR m The m operand is any of r, (HL), (IX+d), or (lY+d), as defined for the analogous RLC instructions. These possible Op Code/operand combinations are specified as follows in the assembled object code:
RR r* RR (HL) RR (IX+d) d 0 RR (IY+d) 0 d 1E 1E FD CB r* CB 1E DD CB 1 CB
Description: The contents of operand m are rotated right 1-bit position through the Carry flag. The content of bit 0 is copied to the Carry flag and the previous content of the Carry flag is copied to bit 7. Bit 0 is the least-significant bit. Instruction RR r RR (HL) RR (IX+d) RR (lY+d) Condition Bits Affected: S is set if result is negative; reset otherwise Z is set if result is zero; reset otherwise H is reset P/V is set if parity even; reset otherwise, N is reset C is data from bit 0 of source register Example: If the contents of the HL register pair are 4343H, and the contents of memory location 4343H and the Carry flag are
M Cycles T States (4, 4) (4, 4, 4, 3) (4, 4, 3, 5, 4, 3) (4, 4, 3, 5, 4, 3)

Bit Tested M Cycles 5 Condition Bits Affected:
S is unknown Z is set if specified Bit is 0; reset otherwise H is set P/V is unknown H is reset C is not affected Example: If the contents of Index Register are 2000H, and bit 6 in memory location 2004H contains 1, at execution of BIT 6, (IY+4H) the Z flag and the F register still contain 0, and bit 6 in memory location 2004H still contains 1. Bit 0 in memory location 2004H is the least-significant bit.

SET b, r

Operation: Op Code: Operands: rb 1 SET b, r
Description: Bit b in register r (any of registers B, C, D, E, H, L, or A) is set. Operands b and r are specified as follows in the assembled object code: Bit M Cycles 2 Condition Bits Affected: None Example: At execution of SET 4, A bit 4 in register A sets. Bit 0 is the leastsignificant bit. b
T States4 MHz E.T. 8 (4, 4) 2.00

SET b, (HL)

Operation: Op Code: Operands: (HL)b 1 SET b, (HL)
Description: Bit b in the memory location addressed by the contents of register pair HL is set. Operand b is specified as follows in the assembled object code: Bit Tested M Cycles 4 Condition Bits Affected: None Example: If the contents of the HL register pair are 3000H, at execution of SET 4, (HL) bit 4 in memory location 3000H is 1. Bit 0 in memory location 3000H is the least-significant bit. b

SET b, (IX+d)

Operation: Op Code: Operands: (IX+d)b 1 SET b, (IX+d)
Description: Bit b in the memory location addressed by the sum of the contents of the IX register pair and the twos complement integer d is set. Operand b is specified as follows in the assembled object code: Bit Tested M Cycles 6 Condition Bits Affected: None Example: If the contents of Index Register are 2000H, at execution of SET 0, (IX + 3H) bit 0 in memory location 2003H is 1. Bit 0 in memory location 2003H is the least-significant bit. b
T States 23 (4, 4, 3, 5, 4, 3)

4 MHz E.T. 5.75

SET b, (IY+d)
Operation: Op Code: Operands: (IY + d) b 1 SET b, (IY + d)
Description: Bit b in the memory location addressed by the sum of the contents of the IY register pair and the twos complement displacement d is set. Operand b is specified as follows in the assembled object code: Bit Tested M Cycles 6 Condition Bits Affected: None Example: If the contents of Index Register IY are 2000H, at execution of SET 0, (IY+3H) bit 0 in memory location 2003H is 1. Bit 0 in memory location 2003H is the least-significant bit. b

RES b, m

Operation: Op Code: Operands: sb 0 RES b, m Operand b is any bit (7 through 0) of the contents of the m operand, (any of r, (HL), (IX+d), or (lY+d)) as defined for the analogous SET instructions. These possible Op Code/operand combinations are assembled as follows in the object code:

110 Undefined Op Code, set the flag 111

T States 12 (4, 4, 4)

Condition Bits Affected: S is set if input data is negative; reset otherwise Z is set if input data is zero; reset otherwise H is reset P/V is set if parity is even; reset otherwise N is reset C is not affected Example: If the contents of register C are 07H, the contents of register B are 10H, and byte 7BH is available at the peripheral device mapped to I/O port address 07H. After execution of IN D, (C) register D contains 7BH.
Operation: Op Code: (HL) (C), B B -1, HL HL + 1 INI
Description: The contents of register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. Register B may be used as a byte counter, and its contents are placed on the top half (A8 through A15) of the address bus at this time. Then one byte from the selected port is placed on the data bus and written to the CPU. The contents of the HL register pair are then placed on the address bus and the input byte is written to the corresponding location of memory. Finally, the byte counter is decremented and register pair HL is incremented. M Cycles 4 Condition Bits Affected: S is unknown Z is set if B1 = 0, reset otherwise H is unknown P/V is unknown N is set C is not affected Example: If the contents of register C are 07H, the contents of register B are 10H, the contents of the HL register pair are 1000H, and byte 7BH is available at the peripheral device mapped to I /O port address 07H. At execution of INI memory location 1000H contains 7BH, the HL register pair contains 1001H, and register B contains 0FH. T States 16 (4, 5, 3, 4) 4 MHz E.T. 4.00
Operation: Op Code: (HL) (C), B B -1, HL HL +1 INIR
Description: The contents of register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. Register B is used as a byte counter, and its contents are placed on the top half (A8 through A15) of the address bus at this time. Then one byte from the selected port is placed on the data bus and written to the CPU. The contents of the HL register pair are placed on the address bus and the input byte is written to the corresponding location of memory. Then register pair HL is incremented, the byte counter is decremented. If decrementing causes B to go to zero, the instruction is terminated. If B is not zero, the PC is decremented by two and the instruction repeated. Interrupts are recognized and two refresh cycles execute after each data transfer.

Operation: Op Code: (C) (HL), B B - 1, HL HL - 1 OTDR
Description: The contents of the HL register pair are placed on the address bus to select a location in memory. The byte contained in this memory location is temporarily stored in the CPU. Then, after the byte counter (B) is decremented, the contents of register C are placed on the bottom half (A0 through A7) of the address bus to select the I/O device at one of 256 possible ports. Register B may be used as a byte counter, and its decremented value is placed on the top half (A8 through A15) of the address bus at this time. Next, the byte to be output is placed on the data bus and written to the selected peripheral device. Then, register pair HL is decremented and if the decremented B register is not zero, the Program Counter (PC) is decremented by two and the instruction is repeated. If B has gone to zero, the instruction is terminated. Interrupts are recognized and two refresh cycles are executed after each data transfer.
Condition Bits Affected: S is unknown Z is set H is unknown P/V is unknown N is set C is not affected Example: If the contents of register C are 07H, the contents of register B are 03H, the contents of the HL register pair are 1000H, and memory locations have the following contents: contains 51H contains A9H contains 03H then at execution of OTDR the HL register pair contain 0FFDH, register B contains zero, and a group of bytes is written to the peripheral device mapped to I/O port address 07H in the following sequence:
0FFEH 0FFFH 1000H 03H A9H 51H

Z8400/84C00

NMOS/CMOS Z80 CPU CENTRAL PROCESSING UNIT

FEATURES

The Extensive Instruction Set.Contains 158 Instructions, Including the 8080A Instructions Set as a Subset. Single 5 Volt Power Supply NMOS Version for Low Cost, High Performance Solutions; CMOS Version for High Performance, Low Power Designs. NMOS Z084004 - 4 MHz Z0840006 - 6.17 MHz Z084008 - 8 MHz CMOS Z0840006 - DC to 6.17 MHz Z84C0008 - DC to 8 MHz Z84C0010 - DC to 10 MHz Z84C0020 - DC to 20 MHz 6 MHz Version can be Operated at 6.144 MHz Clock Speed
The Z80 Microprocessors and Associated Family of Peripherals can be Linked by a Vectored Interrupt System. This System can be Daisy-Chained to Allow Implementation of a Priority Interrupt Scheme. Duplicate Set of Both General-Purpose and Flag Registers Two 16-Bit Index Registers Three Modes of Maskable Interrupts: - Mode 0 - 8080A Similar - Mode 1 - Non-Z80 Environment, Location 38H - Mode 2 - Z80 Family Peripherals, Vectored Interrupts On-Chip Dynamic Memory Refresh Counter

GENERAL DESCRIPTION

The Z8400/Z84C00 CPUs are fourth-generation enhanced microprocessors with exceptional computational power. They offer higher system throughput and more efficient memory utilization than comparable second- and thirdgeneration microprocessors. The speed offerings from MHz suit a wide range of applications which migrate software. The internal registers contain 208 bits of read/ write memory that are accessible to the programmer. These registers include two sets of six general purpose registers which may be used individually as either 8-bit registers or as 16-bit register pairs. In addition, there are two sets of accumulator and flag registers. A group of Exchange instructions makes either set of main or alternate registers accessible to the programmer. The alternate set allows operation in foreground-background mode or it may be reserved for very fast interrupt response. The CPU also contains a Stack Pointer, Program Counter, two index registers, a Refresh register (counter), and an Interrupt register. The CPU is easy to incorporate into a system since it requires only a single +5V power source. All output signals are fully decoded and timed to control standard memory or peripheral circuits; the CPU is supported by an extensive family of peripheral controllers.

PB006301-0301

GENERAL DESCRIPTION (Continued)

8-Bit Data Bus

Data Bus Interface
Instruction Decoder +5V GND Clock CPU Timing Control

Instruction Register

Internal Data Bus
Register Array CPU Timing
8 Systems and CPU Control Outputs

5 CPU Control Inputs

Address Logic and Buffers

16-Bit Address Bus

Figure 1. Z8400/C00 Functional Block Diagram
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