Operation safety

Before installing the motherboard and adding devices on it, carefully read all the manuals that came with the package. Before using the product, make sure all cables are correctly connected and the power cables are not damaged. If you detect any damage, contact your dealer immediately. To avoid short circuits, keep paper clips, screws, and staples away from connectors, slots, sockets and circuitry. Avoid dust, humidity, and temperature extremes. Do not place the product in any area where it may become wet. Place the product on a stable surface. If you encounter technical problems with the product, contact a qualified service technician or your retailer.
P4S800-MX specification summary*
CPU Socket 478 for Intel Pentium 4 Northwood/Willamette processor Intel Hyper-Threading technology ready New power design for next generation Intel Prescott CPU SiS661 FX SiS963L 800/533/400 MHz 2 x 184-pin DDR DIMM sockets for up to 2GB memory Supports PC3200/2700/2100 unbuffered non-ECC DDR DIMMs. 1 x AGP 8X/4X (1.5V only) 3 x PCI SiS Real256E integrated graphics 2 x UltraATA133, PIO Mode 0 ~ 4 ADI AD1888 6-channel audio CODEC Integrated MAC with VIA 6103L 10/100 LAN PHY Super I/O integrated monitoring of CPU/chassis fan rotation and MB/CPU temperature Power loss restart Digital audio via an S/PDIF out inteface 1 x Parallel port 1 x Serial port 1 x Video port 1 x PS/2 keyboard port 1 x PS/2 mouse port 1 x RJ-45 port 4 x USB 2.0/USB 1.1 ports Line In/Line Out/Microphone ports 1 x USB 2.0 connector for additional two USB ports CPU and chassis fan connectors 20-pin/4-pin ATX 12V power connectors CD/AUX audio connectors S/PDIF out connector Front panel audio connector Panel connector Speaker out connector GAME/MIDI connector Power LED connector** (Continued on the next page.) * Specifications are subject to change without notice. ** Present only on PCB versions 1.03 or later.
Chipset Front Side Bus (FSB) Memory
Expansion slots VGA Storage Audio LAN Hardware monitoring Special features Rear panel I/O

Internal I/O

P4S800-MX specification summary
BIOS features 2Mb Flash EEPROM, DMI, PnP features, SM BIOS 2.3, WfM 2.0, ASUS CrashFree BIOS, ASUS EZ Flash, and ASUS C.P.U. (CPU Parameter Recall) PCI 2.2, USB 2.0/1.1 WOL/WOR by PME, Wake on USB KB/Mouse Micro-ATX form factor: 9.6 in x 9.6 in (24.5 cm x 24.5 cm) Device drivers ASUS PC Probe ASUS LiveUpdate ASUS Screensaver Adobe Acrobat Reader Trend Micro PC-cillin 2002 anti-virus software Microsoft DirectX 8.1
Industry standard Manageability Form Factor Support CD contents

About this guide

Conventions used in this guide
To make sure that you perform certain tasks properly, take note of the following symbols used throughout this guide. WARNING: Information to prevent injury to yourself when trying to complete a task. CAUTION: Information to prevent damage to the components when trying to complete a task. IMPORTANT: Information that you MUST follow to complete a task. NOTE: Tips and additional information to aid in completing a task.

Chapter 1

This chapter describes the features of the motherboard. It includes brief descriptions of the motherboard components, and illustrations of the layout, jumper settings, and connectors.

Product introduction

Welcome!
Thank you for buying the ASUS P4S800-MX motherboard! The ASUS P4S800-MX motherboard delivers a host of new features and latest technologies making it another standout in the long line of ASUS quality motherboards! Before you start installing the motherboard, and hardware devices on it, check the items in your package with the list below.

Package contents

ASUS P4S800-MX motherboard Micro-ATX form factor: 9.6 in x 9.6 in (24.5 cm x 24.5 cm) ASUS P4S800-MX series support CD 80-conductor UltraATA IDE cable Ribbon cable for a 3.5-inch floppy drive I/O shield Bag of extra jumper caps User Guide
If any of the above items is damaged or missing, contact your retailer.
Check your P4S800-MX package for the following items.

Special features

Intel 800MHz FSB CPU support
The P4S800-MX comes with a 478-pin surface mount, Zero Insertion Force (ZIF) socket for the Intel Pentium 4 processor and 512/256KB L2 cache on 0.13 micron process. This motherboard supports 800/533/400 MHz system front side bus that allows 6.4GB/s, 4.3GB/s and 3.2GB/s data transfer rates, respectively. The P4S800-MX also supports the Intel Hyper-Threading Technology and the next-generation Intel Prescott CPU. See page 1-8.

SiS661FX/963L chipset

Embedded in this motherboard is the SiS661FX/963L chipset that integrates various SiS-developed technologies to ensure an efficient and reliable computing performance.
The SiS661FX chipset provides a high performance host interface for the Intel Pentium 4 processor, and supports AGP 8X, 800MHz front side bus, and DDR400. The SiS661FX features the SiS HyperStreaming Engine that smartly manages data streams between peripherals, core logic chipsets, front side bus, memory and graphic interfaces. This technology dramatically optimizes and improves the entire computer system performance. Providing I/O and peripheral support is the SiS963L southbridge. The southbridge is a subsystem that integrates various I/O functions including dual-channel ATA133 bus master IDE, USB 2.0/1.1, Ethernet, and audio controllers. The SiS963L provides LPC and AC97 interfaces, and complies with the Advanced Power Management (APM) 1.2 specification. The SiS963L interconnects with the northbridge at up to 1GB/s using the SiS proprietary MuTIOL bus interface.

DDR400 support

The motherboard supports up to 2GB of system memory using PC3200/2700/2100 non-ECC DDR DIMMs to deliver up to 3.2GB/s data transfer rate for the latest 3D graphics, multimedia, and Internet applications. See page 1-10.
Real256E integrated graphics
Embedded in the northbridge is the SiS Real256E integrated graphics with a 256-bit 3D engine and 2D graphics accelerator with a maximum 64MB shared display memory. The Real256E integrated graphics engine incorporates the UltraAGPII technology to provide a faster link between the built-in graphic engine and the northbridge memory controller. This technology boosts VGA throughput to up to 3.2GB/s to bring clearer and sharper images for your multimedia and graphic-intensive applications. The Real256E integrated graphics achieves a maximum resolution of 2048x1526 at 32bpp. See page 2-19.

Integrated 10/100 Mbps LAN controller
Onboard is a VIA 6103L LAN PHY that that interconnects with the SiS963L southbridge LAN controller to fully support 10BASE-T/ 100BASE-TX Ethernet networking. See page 1-17.
SoundMAX digital audio system
The SoundMax Digital Audio System is the industrys highest performance and most reliable audio solution for business professionals, audiophiles, musicians, and gamers. SoundMAX Digital Audio System can output 5.1 channel surround and features state-of-the-art DLS2 MIDI synthesizer with Yamaha DLSbyXG sound set, 5.1 Virtual Theater and supports all major game audio technologies including Microsoft DirectX8.0, Microsoft DirectSound 3D, A3D, MacroFX, ZoomFX, MultiDrive 5.1 and EAX. See page 1-17.
ASUS P4S800-MX motherboard user guide

USB 2.0 connectivity

The P4S800-MX rear panel is equipped with four (4) Universal Serial Bus (USB) ports to connect USB 2.0 devices. A USB header is also available at mid-board to accommodate a USB module for two (2) additional USB ports. The USB ports and header comply with USB 2.0 specification that supports up to 480 Mbps connection speed. This speed advantage over the conventional USB 1.1 (12 Mbps) allows faster Internet connection, interactive gaming, and simultaneous running of high-speed peripherals. USB 2.0 is backward compatible with USB 1.1. See pages 1-17 and 1-20.

ASUS CrashFree BIOS

CrashFree BIOS allows users to restore BIOS data from a floppy diskette even when BIOS code and data are corrupted during upgrade or invaded by a virus. Unlike other competing vendors products, ASUS motherboards now enable users to enjoy this protection feature without the need to pay for an optional ROM. See page 2-6.

ASUS EZ Flash BIOS

With the ASUS EZ Flash, you can easily update the system BIOS even before loading the operating system. No need to use a DOS-based utility or boot from a floppy disk. See page 2-3.

Before you proceed

Take note of the following precautions before you install motherboard components or change any motherboard settings.
1. 2. Unplug the power cord from the wall socket before touching any component. Use a grounded wrist strap or touch a safely grounded object or to a metal object, such as the power supply case, before handling components to avoid damaging them due to static electricity. Hold components by the edges to avoid touching the ICs on them. Whenever you uninstall any component, place it on a grounded antistatic pad or in the bag that came with the component. Before you install or remove any component, ensure that the ATX power supply is switched off or the power cord is detached from the power supply. Failure to do so may cause severe damage to the motherboard, peripherals, and/or components.

3. 4. 5.

Onboard LED
The P4S800-MX comes with a stand-by power LED. When lit, the green LED indicates that the system is ON, in sleep mode, or in soft-off mode, a reminder that you should shut down the system and unplug the power cable before removing or plugging in any motherboard component. The illustration below shows the location of the onboard LED.

SB_PWR1

ON Standby Power

OFF Powered Off

P4S800-MX Onboard LED

Motherboard overview

KBPWR1

24.5cm (9.6in)

1.5.1 Motherboard layout

CPU_FAN1

PS/2KBMS T: Mouse B: Keyboard COM1

+5V (Default)

Socket 478

Super I/O

PARALLEL PORT
DDR DIMM1 (64 bit,184-pin module)
DDR DIMM2 (64 bit,184-pin module)

2Mb ISA

SEC_IDE1

FLOPPY1

PRI_IDE1

USBPW12 USBPW34

+5V (Default) +5VSB

ATX Power Connector

USB2.0 Top: T: USB3 RJ-45 B: USB4
Top:Line In Center:Line Out Below:Mic In

ATX12V1

661FX North Bridge

VIA VT6103

Accelerated Graphics Port (AGP1)
CR2032 3V Lithium Cell CMOS Power

USBPWR12 USBPWR34

USB1 USB2

CLRTC1

Clear CMOS Normal (Default)

AD1888 CODEC

PCI1 PCI2

SiS 963L Chipset

SPEAKER1 PLED1 F_PANEL1

FP_AUDIO1

CHA_FAN1 USBPW56 USB56

F_PANEL1

USBPW56

PLED+ NC PLED-

Power LED

ATX Power Switch*

IDE_LED
* Requires an ATX power supply.
IDE_LED+ IDE_LEDGround Reset

PLED+ PLEDPWR GND

Reset SW
1.5.2 Placement direction
When installing the motherboard, make sure that you place it into the chassis in the correct orientation. The edge with external ports goes to the rear part of the chassis as indicated in the image below.

1.5.3 Screw holes

Place eight (8) screws into the holes indicated by circles to secure the motherboard to the chassis.
Do not overtighten the screws! Doing so may damage the motherboard.
Place this side towards the rear of the chassis
Central Processing Unit (CPU)

Light Blue Lime Pink Headphone /2-Speaker Line In Line Out Mic In 4-Speaker Line In Front Speaker Out Rear Speaker Out 6-Speaker Bass/Center Front Speaker Out Rear Speaker Out
Windows 98SE only supports 2-channel speaker configuration.
7. USB 2.0 ports 1 and 2. These two 4-pin Universal Serial Bus (USB) ports are available for connecting USB 2.0 devices. 8. USB 2.0 ports 3 and 4. These two 4-pin Universal Serial Bus (USB) ports are available for connecting USB 2.0 devices. 9. VGA port. This port connects a VGA compatible monitor. 10. Serial port. This 9-pin COM port is for pointing devices or other serial devices. 11. PS/2 keyboard port. This purple connector is for a PS/2 keyboard.
1.10.2 Internal connectors
1. IDE connectors (40-1 pin PRI_IDE1, SEC_IDE1) This connector supports the provided UltraATA133 IDE hard disk ribbon cable. Connect the cables blue connector to the primary (recommended) or secondary IDE connector, then connect the gray connector to the UltraATA133 slave device (hard disk drive) and the black connector to the UltraATA133 master device.
1. 2. Follow the hard disk drive documentation when setting the device in master or slave mode. Pin 20 on each IDE connector is removed to match the covered hole on the UltraATA cable connector. This prevents incorrect orientation when you connect the cables. The hole near the blue connector on the UltraATA cable is intentional.

P4S800-MX IDE Connectors

2. Floppy disk drive connector (34-1 pin FLOPPY1) This connector supports the provided floppy drive ribbon cable. After connecting one end to the motherboard, connect the other end to the floppy drive. (Pin 5 is removed to prevent incorrect insertion when using ribbon cables with pin 5 plug).
NOTE: Orient the red markings on the floppy ribbon cable to PIN 1.
P4S800-MX Floppy Disk Drive Connector
NOTE: Orient the red markings (usually zigzag) on the IDE ribbon cable to PIN 1.
3. ATX power connectors (20-pin ATXPWR1, 4-pin ATX12V1) These connectors connect to an ATX 12V power supply. The plugs from the power supply are designed to fit these connectors in only one orientation. Find the proper orientation and push down firmly until the connectors completely fit. In addition to the 20-pin ATXPWR connector, this motherboard requires that you connect the 4-pin ATX +12V power plug to provide sufficient power to the CPU.

Make sure that your ATX 12V power supply can provide 8A on the +12V lead and at least 1A on the +5-volt standby lead (+5VSB). The minimum recommended wattage is 230W, or 300W for a fully configured system. The system may become unstable and may experience difficulty powering up if the power supply is inadequate.

+12V DC GND

ATXPWR1
+5.0VDC +5.0VDC -5.0VDC COM COM COM PS_ON# COM -12.0VDC +3.3VDC
+12V DC +12.0VDC GND +5VSB
PWR_OK COM +5.0VDC COM +5.0VDC COM +3.3VDC +3.3VDC
P4S800-MX ATX Power Connector
4. Front panel audio connector (10-1 pin FP_AUDIO1) This is an interface for the front panel cable that allows convenient connection and control of audio devices. Be default, the pins labeled LINE OUT_R/BLINE_OUT_R and the pins LINE OUT_L/BLINE_OUT_L are shorted with jumper caps. Remove the caps only when you are connecting the front panel audio cable.

AGND +5VA BLINE_OUT_R

MIC2 MICPWR Line out_R NC Line out_L
P4S800-MX Front Panel Audio Connector

BLINE_OUT_L

5. CPU and chassis fan connectors (3-pin CPU_FAN1, CHA_FAN1) The fan connectors support cooling fans of 350mA~740mA (8.88W max.) or a total of 1A~2.22A (26.64W max.) at +12V. Connect the fan cables to the fan connectors on the motherboard, making sure that the black wire of each cable matches the ground pin of the connector.
Do not forget to connect the fan cables to the fan connectors. Lack of sufficient air flow within the system may damage the motherboard components. These are not jumpers! DO NOT place jumper caps on the fan connectors!

GND +12V Rotation

CHA_FAN1
P4S800-MX 12-Volt Fan Connectors
6. USB header (10-1 pin USB56) If the USB ports on the rear panel are inadequate, a USB header is available for additional USB ports. Connect the USB cable of an optional USB 2.0 module to this header. You may install the USB module in the chassis front panel. The module has two USB 2.0 ports for connecting next generation USB peripherals such as high resolution cameras, scanners, and printers.

USB+5V USB_P5USB_P5+ GND

P4S800-MX USB 2.0 Header
The USB module is purchased separately.

USB+5V USB_P6USB_P6+ GND NC
7. Digital audio connector (4-1 pin SPDIF_OUT1) An S/PDIF Out connector is available for an S/PDIF audio module. Connect one end of the S/PDIF audio module cable to this connector and the other end to the S/PDIF module.

SPDIF_OUT1

SPDIFOUT GND
P4S800-MX Digital Audio Connector The S/PDIF module is purchased separately.
8. Internal audio connectors (4-pin AUX1, CD1) These connectors allow you to receive stereo audio input from sound sources such as a CD-ROM, TV tuner, or MPEG card.

AUX1 (White) CD1 (Black)

Left Audio Channel Ground Ground Right Audio Channel
P4S800-MX Internal Audio Connectors
9. Speaker out connector (4-pin SPEAK1) This connector connects to the case-mounted speaker and allows you to hear system beeps and warnings.

SPEAKER1

+5V GND GND Speak Out
P4S800-MX Speaker Out Connector
10. GAME/MIDI connector (16-1 pin GAME1) This connector supports a GAME/MIDI module. Connect the GAME/MIDI cable with yellow connector to the yellow header onboard. The GAME/MIDI port on the module connects a joystick or a game pad for playing games, and MIDI devices for playing or editing audio files.
GAME1 P4S800-MX Game Connector
The GAME module is purchased separately.
+5V J1B1 J1CX GND GND J1CY J1B2 +5V
+5V J2B1 J2CX MIDI_OUT J2CY J2B2 MIDI_IN
11. Power LED Lead (3-1 pin PLED1) This 3-1 pin connector is for the system power LED. Connect the 3-pin power LED cable from the system chassis to this connector. The LED lights up when you turn on the system power, and blinks when the system is in sleep mode.
The power LED lead (PLED1) is present only on PCB versions 1.03 or later.

P4S800-MX PLED Setting

12. System panel connector (10-1 pin F_PANEL1) This connector accommodates several system front panel functions.
Power LED ATX Power Switch*
IDE_LED P4S800-MX Front Panel Audio Connector
Power LED Lead (2-pin PWR_LED) This 2-pin connector connects to the system power LED. The LED lights up when you turn on the system power, and blinks when the system is in sleep mode. If your motherboard package comes with a 2-pin to 3-pin power LED converter, connect the 2-pin plug to this connector, and the other end to the 3-pin power LED plug from the system chassis.
Power Switch / Soft-Off Switch Lead (2-pin PWR_BTN) This connector connects a switch that controls the system power. Pressing the power switch turns the system between ON and SLEEP, or ON and SOFT OFF, depending on the BIOS or OS settings. Pressing the power switch while in the ON mode for more than 4 seconds turns the system OFF.
IDE LED Lead (2-pin IDE_LED) This 2-pin connector supplies power to the hard disk drive activity LED. The read or write activities of any device connected to the primary or secondary IDE connector cause this LED to light up.

USB Legacy Support [Auto]
This motherboard supports Universal Serial Bus (USB) devices. The default of [Auto] allows the system to detect a USB device at startup. If detected, the USB controller legacy mode is enabled. If not detected, the USB controller legacy mode is disabled. When you set this field to [Disabled], the USB controller legacy mode is disabled whether or not you are using a USB device. Configuration options: [Disabled] [Enabled] [Auto]
OS/2 Onboard Memory > 64M [Disabled]
When using OS/2 operating systems with installed DRAM of greater than 64MB, you need to set this option to [Enabled]. Otherwise, leave to the default setting [Disabled]. Configuration options: [Disabled] [Enabled]

2.4.1 Chip Configuration

SDRAM Configuration [By SPD]
This parameter allows you to set the optimal timings for items 25, depending on the memory modules that you are using. The default setting is [By SPD], which configures items 25 by reading the contents in the SPD (Serial Presence Detect) device. The EEPROM on the memory module stores critical information about the module, such as memory type, size, speed, voltage interface, and module banks. Configuration options: [User Defined] [By SPD]
The SDRAM parameters (items 2~5) become configurable only when you set the SDRAM Configuration to [User Defined].
SDRAM CAS Latency (value depends on SDRAM SPD)
This item controls the latency between the SDRAM read command and the time the data actually becomes available. Configuration options: [2.5T] [2T] [1.5T] [3T]
SDRAM RAS to CAS Delay (value depends on SDRAM SPD)
This item controls the latency between the DDR SDRAM active command and the read/write command. Configuration options: [3T] [2T] [4T]
SDRAM RAS Precharge Time (value depends on SDRAM SPD)
This item controls the idle clocks after issuing a precharge command to the DDR SDRAM. Configuration options: [3T] [2T] [4T]
SDRAM Active Precharge Delay (value depends on SDRAM SPD)
This item controls the number of DDR SDRAM clocks used for DDR SDRAM parameters. Configuration options: [6T] [7T] [5T] [9T]
Chipset Clock Mode [Synchronous]
When set to [Synchronous], AGP/PCI frequency is coordinated with the CPU frequency. When set to [Asynchronous], AGP/PCI frequency is not adjusted according to the CPU frequency. Configuration options: [Synchronous] [Asynchronous]

SDRAM Command Lead-off Time [Auto]
Configuration options: [Auto] [2T] [1T]
Graphics Aperture Size [64MB]
This feature allows you to select the size of mapped memory for AGP graphic data. Configuration options: [4MB] [8MB] [16MB] [32MB] [64MB] [128MB] [256MB]
AGP 3.0 Capability [8X Mode]
This motherboard supports the AGP 8X interface that transfers video data at 2.12GB/s. The configuration options vary depending on the speed of AGP card installed. If an AGP 4X card is installed, configuration options will be [4X Mode]. The setting [8X Mode] will be the default if an AGP 8X card is installed. AGP 8X is backward-compatible so you may keep the [4X Mode] setting, however the AGP interface will only provide a peak data throughput of 1066MB/s even if you are using an AGP 8X card. Configuration options: [8X Mode] [4X Mode]
AGP Fast Write Capability [Enabled]
This field enables or disables the AGP 4x Fast Write Capability feature. Configuration options: [Enabled] [Disabled]
Video Memory Cache Mode [UC]
USWC (uncacheable, speculative write combining) is a new cache technology for the video memory of the processor. It can greatly improve the display speed by caching the display data. You must set this to UC (uncacheable) if your display card does not support this feature, otherwise the system may not boot. Configuration options: [UC] [USWC]

Onboard VGA [Enabled]

This item allows you to enable or disable the onboard VGA controller. Configuration options: [Enabled] [Disabled]
Onboard VGA Shared Memory Size [32M]
This field allows you to set the onboard VGA memory size with the currently installed system memory. Configuration options: [32M] [64M]
Delay Transaction [Enabled]
This field enables or disables the PCI delay transaction function. Configuration options: [Enabled] [Disabled]

Onboard PCI IDE [Both]

This field allows you to enable either the primary IDE channel or secondary IDE channel, or both. You can also set both channels to [Disabled]. Configuration options: [Both] [Primary] [Secondary] [Disabled]
IDE Bus Master Support [Enabled]
This item controls the IDE Bus Master support for non-Windows operating systems. Configuration options: [Enabled] [Disabled]
2.4.2 I/O Device Configuration
Floppy Disk Access Control [R/W]
When set to [Read Only], this parameter protects files from being copied to floppy disks by allowing reads from, but not writes to, the floppy disk drive. The default setting [R/W] allows both reads and writes. Configuration options: [R/W] [Read Only]

Onboard Serial Port 1 [3F8H/IRQ4]
This field allows you to set the addresses for the onboard serial connector. Configuration options: [3F8H/IRQ4] [2F8H/IRQ3] [3E8H/IRQ4] [2E8H/IRQ10] [Disabled]
Onboard Parallel Port [378H/IRQ7]
This field allows you to set the address of the onboard parallel port connector. If you disable this field, the Parallel Port Mode and ECP DMA Select configurations are not available. Configuration options: [Disabled] [378H/IRQ7] [278H/IRQ5]
Parallel Port Mode [ECP+EPP]
This field allows you to set the operation mode of the parallel port. [Normal] allows normal-speed operation but in one direction only; [EPP] allows bidirectional parallel port operation; [ECP] allows the parallel port to operate in bidirectional DMA mode; [ECP+EPP] allows normal speed operation in a two-way mode. Configuration options: [Normal] [EPP] [ECP] [ECP+EPP]

ECP DMA Select [3]

This field allows you to configure the parallel port DMA channel for the selected ECP mode. This selection is available only if you select [ECP] or [ECP+EPP] in Parallel Port Mode above. Configuration options: [1] [3]
Onboard Game Port [200H-207H]
This field sets the I/O address for the game port. Configuration options: [Disabled] [200H-207H] [208H-20FH]
Onboard MIDI I/O [Disabled]
This field sets the I/O address for the MIDI I/O port. Configuration options: [Disabled] [330H-331H] [300H-301H]

2.4.3 PCI Configuration

Slot 1, Slot 2, Slot 3 IRQ [Auto]
These fields automatically assign the IRQ for each PCI slot. The default setting for each field is [Auto], which utilizes auto-routing to determine IRQ assignments. Configuration options: [Auto] [NA] [3] [4] [5] [7] [9] [10] [11] [12] [14] [15]
PCI/VGA Palette Snoop [Disabled]
Some non-standard VGA cards, like graphics accelerators or MPEG video cards, may not show colors properly. Setting this field to [Enabled] corrects this problem. If you are using standard VGA cards, leave this field to the default setting [Disabled]. Configuration options: [Disabled] [Enabled]

PCI Latency Timer [32]

Leave this field to the default setting [32] for best performance and stability.
Primary VGA BIOS [PCI VGA Card]
This field allows you to select the primary graphics card. Configuration options: [PCI VGA Card] [AGP VGA Card] [Onboard VGA]

Power Up On PCI Device [Disabled]
When set to [Enabled], this parameter allows you to turn on the system through a PCI LAN or modem card. This feature requires an ATX power supply that provides at least 1A on the +5VSB lead. Configuration options: [Disabled] [Enabled]
Power On By PS/2 Keyboard [Disabled]
This parameter allows you to use specific keys on the keyboard to turn on the system. This feature requires an ATX power supply that provides at least 1A on the +5VSB lead. Configuration options: [Disabled] [Space Bar] [Ctrl-Esc] [Power Key]
Automatic Power Up [Disabled]
This allows an unattended or automatic system power up. You may configure your system to power up at a certain time of the day by selecting [Everyday] or at a certain time and day by selecting [By Date]. Configuration options: [Disabled] [Everyday] [By Date]

2.5.2 Hardware Monitor

CPU Temperature MB Temperature
The onboard hardware monitor automatically detects and displays the motherboard and CPU temperatures. Select [Ignore] to disable the MB or CPU temperature auto-detect function.
CPU Fan Speed [xxxxRPM] or [N/A] Chassis Fan Speed [xxxxRPM] or [N/A]
The onboard hardware monitor automatically detects and displays the CPU, chassis, and power fan speeds in rotations per minute (RPM). If any of the fans is not connected to the motherboard, the specific field shows N/A.
VCORE Voltage, +3.3V Voltage, +5V Voltage, +12V Voltage
The onboard hardware monitor automatically detects the voltage output through the onboard voltage regulators.
If any of the monitored items is out of range, the following error message appears: Hardware Monitor found an error. Enter Power setup menu for details. You will then be prompted to Press F1 to continue or DEL to enter SETUP.

Boot Menu

Boot Sequence
The Boot menu allows you to select among the four possible types of boot devices listed using the up and down arrow keys. By using the <+> or <Space> key, you can promote devices and by using the <-> key, you can demote devices. Promotion or demotion of devices alters the priority which the system uses to search for a boot device on system power up. Configuration fields include Removable Devices, IDE Hard Drive, ATAPI CD-ROM, and Other Boot Device.
Removable Device [Legacy Floppy]
Configuration options: [Disabled] [Legacy Floppy] [LS-120] [ZIP] [ATAPIMO] [USB FDD] [USB ZIP]

IDE Hard Drive

This field allows you to select which IDE hard disk drive to use in the boot sequence. Pressing [Enter] will show the product IDs of all connected IDE hard disk drives.

ATAPI CD-ROM

This field allows you to select which ATAPI CD-ROM drive to use in the boot sequence. Pressing [Enter] will show the product IDs of all your connected ATAPI CD-ROM drives.
Other Boot Device Select [INT18 Device (Network)]

Load Setup Defaults

This option allows you to load the default values for each of the parameters on the Setup menus. When you select this option or if you press <F5>, a confirmation window appears. Select [Yes] to load default values. Select Exit & Save Changes or make other changes before saving the values to the non-volatile RAM.

Discard Changes

This option allows you to discard the selections you made and restore the previously saved values. After selecting this option, a confirmation appears. Select [Yes] to discard any changes and load the previously saved values.

Save Changes

This option saves your selections without exiting the Setup program. You can then return to other menus and make further changes. After you select this option, a confirmation window appears. Select [Yes] to save changes to the non-volatile RAM.

Chapter 3

This chapter describes the contents of the support CD that comes with the motherboard package.

Software support

Install an operating system
This motherboard supports Windows 98SE/ME/2000/XP operating system (OS). Always install the latest OS version and corresponding updates so you can maximize the features of your hardware.
Because motherboard settings and hardware options vary, use the setup procedures presented in this chapter for general reference only. Refer to your OS documentation for more information.

Support CD information

The support CD that came with the motherboard contains useful software and several utility drivers that enhance the motherboard features.
The contents of the support CD are subject to change at any time without notice. Visit the ASUS website for updates.
3.2.1 Running the support CD
To begin using the support CD, simply insert the CD into your CD-ROM drive. The CD automatically displays the Drivers menu if Autorun is enabled in your computer. Click on an item to install.
If Autorun is NOT enabled in your computer, browse the contents of the support CD to locate the file ASSETUP.EXE from the BIN folder. Double-click the ASSETUP.EXE to run the CD.

3.2.2 Drivers menu

TS2G~16GCFX500

Description
Transcend CFAST cards are designed to satisfy high performance requirements using a SATA 3Gb/s

CFAST Card

Features
RoHS compliant CFast Specification Version 1.0 Compliant Power Supply: 3.3V5% Operating Temperature: 0 C to 70 C Storage Temperature: -40 C to 85 C Humidity (Non condensation): 0% to 95% Built-in 8-bit/512Byte ECC (Error Correction Code) functionality ensures highly reliable of data transfer. Global wear-leveling algorithm eliminate excessive write operation and extends product life. Suppot StaticDataRefresh & EarlyRetirement technology to monitor error bit level and react before data is corrupted.

o o o o

interface. As a removable device, it is easier to plug and remove in space-limited applications; such as
thin-clients or industrial PCs. Compliant with CFAST 1.0 standard, CFAST is your best choice as an embedded SATA storage solution.

Placement

Support S.M.A.R.T (Self-defined) Support Security Command Fully compatible with devices and OS that support the SATA 3Gb/s standard Non-volatile SLC Flash Memory for outstanding data retention

Dimensions

A B C D

Millimeters

42.8 36.4 3.3 0.6

Inches

1.685 1.433 0.13 0.02
Transcend Information Inc.

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Specifications

Physical Specification

Form Factor Storage Capacities Length Dimensions (mm) Width Height Input Voltage Weight Connector CFAST 2GB~16 GB 42.8 0.1 36.4 0.15 3.3 0.1 3.3V 5% TBD CFAST connector
Environmental Specifications
Operating Temperature Storage Temperature Humidity Operating Non-Operating 0 to 70 - 40 to 85 0% to 95% (Non-condensing) 0% to 95% (Non-condensing)

Regulations

Compliance CE, FCC and BSMI

Performance

Model P/N TS2GCFX500 TS4GCFX500 TS8GCFX500 TS16GCFX500 Read -56 MB/s 102 MB/s 108 MB/s Write -49MB/s 88MB/s 91MB/s
Random Read -50 MB/s 83MB/s 89 MB/s
Random Write -12 MB/s 17 MB/s 18 MB/s
Note: 25 , test on ASUS P4S800-MX, 1GB RAM, Windows XP Version 2002 SP2, benchmark utility HDBENCH (version 3.4006), copied file 1GB.

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Actual Capacity
Model P/N TS2GCFX500 TS4GCFX500 TS8GCFX500 TS16GCFX500 User Max. LBA 3,865,680 7,732,368/ 15,465,344 30,932,992 Cylinder 3,835 7,671 15,343 16,383

Head 16 15

Sector 63 63

Power Requirements

Input Voltage Mode Write(peak) Power Consumption Read(peak) Idle(peak) 3.3V 5% Max. (mA) 141
SHOCK & Vibration Test
Condition Mechanical Shock Test Vibration Test 1500G, 0.5ms, 3 axis 20G (Peak-to-Peak) 20Hz to 2000Hz (Frequency) Standard IEC 60068-2-27 IEC 60068-2-6

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Package Dimensions
Below figure illustrates the Transcend CFast. All dimensions are in mm.

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Pin Assignments
Pin No. S1 S2 S3 S4 S5 S6 S7 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 Pin Name 7-pin Signal Segment GND A+ AGND BB+ GND 17-pin Power Segment CDI GND NC NC NC NC GND NC NC NC NC NC 3.3V 3.3V GND GND CDO

Pin Layout

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Block Diagram

CFASTTM Interface

SATA SSD CTL

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Reliability

Wear-Leveling algorithm
The controller supports static/dynamic wear leveling. When the host writes data, the controller will find and use the block with the lowest erase count among the free blocks. This is known as dynamic wear leveling. When the free blocks' erase count is higher than a threshold value plus data blocks', it will activate the static wear leveling, replacing the not so frequently used user blocks with the high erase count free blocks. ECC algorithm Using 8bit BCH Error Correction Code with each channel, the controller can correct 8 random bits per 512 byte data sector for SLC NAND flash. The hardware executes parity generation and error detection/correction features. StaticDataRefresh Technology Normally, ECC engine corrections are taken place without affecting the host normal operations. As time passes by, the number of error bits accumulated in the read transaction exceeds the correcting capability of the ECC engine, resulting in corrupted data being sent to the host. To prevent this, the controller monitors the error bit levels at each read operation; when it reaches the preset threshold value, the controller automatically performs data refresh to restore the correct charge levels in the cell. This implementation practically restores the data to its original, error-free state, and hence, lengthening the life of the data. EarlyRetirement Technology The StaticDataRefresh feature functions well when the cells in a block are still healthy. As the block ages over time, it cannot reliably store charge anymore, EarlyRetirement enters the scene. EarlyRetirement works by moving the static data to another block (a health block) before the previously used block becomes completely incapable of holding charges for data. When the charge loss error level exceeds another threshold value (higher from that for StaticDataRefresh), the controller automatically moves its data to another block. In addition, the original block is then marked as a bad block, which prevents its further use, and thus the block enters the state of EarlyRetirement. Note that, through this process, the incorrect data are detected and effectively corrected by the ECC engine, thus the data in the new block is stored error-free.

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Out of bank signaling
There shall be three Out Of Band (OOB) signals used/detected by the Phy: COMRESET, COMINIT, and COMWAKE. COMINIT, COMRESET and COMWAKE OOB signaling shall be achieved by transmission of either a burst of four Gen1 ALIGNP primitives or a burst composed of four Gen1 Dwords with each Dword composed of four D24.3 characters, each burst having a duration of 160 UIOOB. Each burst is followed by idle periods (at common-mode levels), having durations as depicted in Figure 4 and Table 2.

Figure 4 : OOB signals

Table 2 : OOB signal times

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COMRESET
COMRESET always originates from the host controller, and forces a hardware reset in the device. It is indicated by transmitting bursts of data separated by an idle bus condition. The OOB COMRESET signal shall consist of no less than six data bursts, including inter-burst temporal spacing. The COMRESET signal shall be: 1) Sustained/continued uninterrupted as long as the system hard reset is asserted, or 2) Started during the system hardware reset and ended some time after the negation of system hardware reset, or 3) Transmitted immediately following the negation of the system hardware reset signal. The host controller shall ignore any signal received from the device from the assertion of the hardware reset signal until the COMRESET signal is transmitted. Each burst shall be 160 Gen1 UIs long (106.7 ns) and each inter-burst idle state shall be 480 Gen1 UIs long (320 ns). A COMRESET detector looks for four consecutive bursts with 320 ns spacing (nominal). Any spacing less than 175 ns or greater than 525 ns shall invalidate the COMRESET detector output. The COMRESET interface signal to the Phy layer shall initiate the Reset sequence shown in Figure 5 below. The interface shall be held inactive for at least 525 ns after the last burst to ensure far-end detector detects the negation properly.
Figure 5: Comreset sequence

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Description: 2. Some condition in the host causes the host to issue COMRESET
1. Host/device is powered and operating normally with some form of active communication.
3. Host releases COMRESET. Once the condition causing the COMRESET is released, the host releases the COMRESET signal and puts the bus in a quiescent condition. 4. Device issues COMINIT When the device detects the release of COMRESET, it responds with a COMINIT. This is also the entry point if the device is late starting. The device may initiate communications at any time by issuing a COMINIT. 5. Host calibrates and issues a COMWAKE. 6. Device responds The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional). Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the ALIGN sequence starting at the device's highest supported speed. After ALIGNP Dwords have been sent for 54.6us (2048 nominal Gen1 Dword times) without a response from the host as determined by detection of ALIGNP primitives received from the host, the device assumes that the host cannot communicate at that speed. If additional speeds are available the device tries the next lower supported speed by sending ALIGNP Dwords at that rate for 54.6 us (2048 nominal Gen1 Dword times.) This step is repeated for as many slower speeds as are supported. Once the lowest speed has been reached without response from the host, the device enters an error state. 7. Host locks after detecting the COMWAKE, the host starts transmitting D10.2 characters at its lowest supported rate. Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at the same speed as received. A host shall be designed such that it acquires lock in 54.6us (2048 nominal Gen1 Dword times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword times) after detecting the release of COMWAKE to receive the first ALIGNP. This ensures interoperability with multi-generational and synchronous designs. If no ALIGNP is received within 873.8 us (32768 nominal Gen1 Dword times) the host restarts the power-on sequence repeating indefinitely until told to stop by the Application layer. 8. Device locks the device locks to the ALIGN sequence and, when ready, sends SYNCP indicating it is ready to start normal operation. 9. Upon receipt of three back-to-back non-ALIGNP primitives, the communication link is established and normal operation may begin.

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COMINIT
COMINIT always originates from the drive and requests a communication initialization. It is electrically identical to the COMRESET signal except that it originates from the device and is sent to the host. It is used by the device to request a reset from the host in accordance to the sequence shown in Figure 6, below.
Figure 6 : cominit sequence Description: 1. Host/device are powered and operating normally with some form of active communication. 2. Some condition in the device causes the device to issues a COMINIT 3. Host calibrates and issues a COMWAKE. 4. Device responds The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional). Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the ALIGN sequence starting at the device's highest supported speed. After ALIGNP Dwords have been sent for 54.6 us (2048 nominal Gen1 Dword times) without a response from the host as determined by detection of ALIGNP primitives received from the host, the device assumes that the host cannot communicate at that speed. If additional speeds are available the device tries the next lower supported speed by sending ALIGNP Dwords at that rate for 54.6 us (2048 nominal Gen1 Dword

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without response from the host, the device enters an error state.
times.) This step is repeated for as many slower speeds as are supported. Once the lowest speed has been reached
5. Host locks after detecting the COMWAKE, the host starts transmitting D10.2 characters at its lowest supported rate. Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at the same speed as received. A host shall be designed such that it acquires lock in 54.6 us (2048 nominal Gen1 Dword times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword times) after detecting the release of COMWAKE to receive the first ALIGNP. This ensures interoperability with multi-generational and synchronous designs. If no ALIGNP is received within 873.8 us (32768 nominal Gen1 Dword times) the host restarts the power-on sequence repeating indefinitely until told to stop by the Application layer. 6. Device locks the device locks to the ALIGN sequence and, when ready, sends SYNCP indicating it is ready to start normal operation. 6. Upon receipt of three back-to-back non-ALIGNP primitives, the communication link is established and normal operation may begin. Power on sequence timing diagram The following timing diagrams and descriptions are provided for clarity and are informative. The state diagrams provided in section 8.4 comprise the normative behavior specification and is the ultimate reference.

Figure 7: power on sequence

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Description: 1. Host/device power-off - Host and device power-off.
2. Power is applied - Host side signal conditioning pulls TX and RX pairs to neutral state (common mode voltage). 3. Host issues COMRESET 4. Host releases COMRESET. Once the power-on reset is released, the host releases the COMRESET signal and puts the bus in a quiescent condition. 5. Device issues COMINIT When the device detects the release of COMRESET, it responds with a COMINIT. This is also the entry point if the device is late starting. The device may initiate communications at any time by issuing a COMINIT. 6. Host calibrates and issues a COMWAKE. 7. Device responds The device detects the COMWAKE sequence on its RX pair and calibrates its transmitter (optional). Following calibration the device sends a six burst COMWAKE sequence and then sends a continuous stream of the ALIGN sequence starting at the device's highest supported speed. After ALIGNP primitives have been sent for 54.6 us (2048 nominal Gen1 Dword times) without a response from the host as determined by detection of ALIGNP primitives received from the host, the device assumes that the host cannot communicate at that speed. If additional speeds are available the device tries the next lower supported speed by sending ALIGNP primitives at that rate for 54.6 us (2048 nominal Gen1 Dword times.) This step is repeated for as many slower speeds as are supported. Once the lowest speed has been reached without response from the host, the device shall enter an error state. 8. Host locks after detecting the COMWAKE, the host starts transmitting D10.2 characters at its lowest supported rate. Meanwhile, the host receiver locks to the ALIGN sequence and, when ready, returns the ALIGN sequence to the device at the same speed as received. A host shall be designed such that it acquires lock in 54.6 us (2048 nominal Gen1 Dword times) at any given speed. The host should allow for at least 873.8 us (32768 nominal Gen1 Dword times) after detecting the release of COMWAKE to receive the first ALIGNP. This insures interoperability with multi-generational and synchronous designs. If no ALIGNP is received within 873.8 us (32768 nominal Gen1 Dword times) the host restarts the power-on sequence repeating indefinitely until told to stop by the Application layer. 9. Device locks the device locks to the ALIGN sequence and, when ready, sends the SYNCP primitive indicating it is ready to start normal operation. 10. Upon receipt of three back-to-back non-ALIGNP primitives, the communication link is established and normal operation may begin.

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ATA command register This table with the following paragraphs summarizes the ATA command set. Support ATA/ATAPI Command General Feature Set
EXECUTE DIAGNOSTICS FLUSH CACHE IDENTIFY DEVICE READ DMA READ MULTIPLE READ SECTOR(S) READ VERIFY SECTOR(S) SET FEATURES SET MULTIPLE MODE WRITE DMA WRITE MULTIPLE WRITE SECTOR(S) NOP READ BUFFER WRITE BUFFER 90h E7h ECh C8h C4h 20h 40h or 41h EFh C6h CAh C5h 30h 00h E4h E8h E5h or 98h E3h or 97h E1h or 95h E6h or 99h E2h or 96h E0h or 94h F1h F2h F3h F4h F5h F6h B0h B0h B0h B0h B0h B0h F8h F9h F9h F9h F9h F9h

Protocol

Device diagnostic Non-data PIO data-In DMA PIO data-In PIO data-In Non-data Non-data Non-data DMA PIO data-out PIO data-out Non-data PIO data-In PIO data-out Non-data Non-data Non-data Non-data Non-data Non-data PIO data-out PIO data-out Non-data PIO data-out Non-data PIO data-out Non-data Non-data Non-data Non-data Non-data PIO data-In Non-data Non-data PIO data-out Non-data Non-data PIO data-out
Power Management Feature Set
CHECK POWER MODE IDLE IDLE IMMEDIATE SLEEP STANDBY STANDBY IMMEDIATE
Security Mode Feature Set
SECURITY SET PASSWORD SECURITY UNLOCK SECURITY ERASE PREPARE SECURITY ERASE UNIT SECURITY FREEZE LOCK SECURITY DISABLE PASSWORD

SMART Feature Set

SMART Disable Operations SMART Enable/Disable Autosave SMART Enable Operations SMART Return Status SMART Execute Off-Line Immediate SMART Read Data
Host Protected Area Feature Set
Read Native Max Address Set Max Address Set Max Set Password Set Max Lock Set Max Freeze Lock Set Max Unlock

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ATA Command Specifications

FLUSH CACHE (E7h)

This command is used by the host to request the device to flush the write cache. If there is data in the write cache, that data shall be written to the media. The BSY bit shall remain set to one until all data has been successfully written or an error occurs.

IDENTIFY DEVICE (ECh)

This commands read out 512Bytes of drive parameter information. Parameter Information consists of the arrangement and value as shown in the following table. This command enables the host to receive the Identify Drive Information from the device.

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Word Address 6 7-10-23-26 27-Word Address 56 57-60-Default Value 044Ah XXXXh 0000h 00XXh 0000h 0240h XXXXh XXXXh 0000h aaaa 0002h 0002h 0004h aaaa aaaa 8001h Default Value 0000h 0F00h 4000h 0200h 0000h 0007h XXXXh 00XXh XXXXh XXXXh 01XXh XXXXh 0000h 0007h 0003h 0078h 0078h Total Bytes Total Bytes 2 Reserved Capabilities Capabilities PIO data transfer cycle timing mode Obsolete Field Validity Current numbers of cylinders Current numbers of heads Current sectors per track General configuration Default number of cylinders Reserved Default number of heads Obsolete Obsolete Default number of sectors per track
Identify Device Information Default Value
Data Field Type Information
Number of sectors per card (Word 7 = MSW, Word 8 = LSW) Obsolete Serial number in ASCII (Right Justified) Obsolete Obsolete Obsolete Firmware revision in ASCII. Big Endian Byte Order in Word Model number in ASCII (Left Justified) Big Endian Byte Order in Word Maximum number of sectors on Read/Write Multiple command Data Field Type Information
Current capacity in sectors (LBAs)(Word 57 = LSW, Word 58 = MSW) Multiple sector setting Total number of sectors addressable in LBA Mode Reserved Multiword DMA transfer. Supports MDMA Mode 0,1,and 2 Advanced PIO modes supported Minimum Multiword DMA transfer cycle time per word. In PC Card modes this value shall be 0h Recommended Multiword DMA transfer cycle time. In PC Card modes this value shall be 0h

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69-77-85-Word Address 93-129-165-175 176-255 0078h 0078h 0000h 0006h 000h 0080h 0000h 742Bh 550Ch 4002h XXXXh 047Fh 0001h 0000h 0000h FFFEh Default Value 0000h 0001h 0000h 81F4h 0000h 0000h 0000h 0000h 0000h 0000h Total Bytes Reserved Security status Vendor unique bytes Power requirement description Reserved Key management schemes supported Reserved Serial ATA capacities Support Serial ATA Gen1 Support Serial ATA Gen2 Reserved Minor version number (ATAPI-7) Minor version number Command sets supported 0 Command sets supported 1 Command sets supported 2 Features/command sets enabled Ultra DMA Mode Supported and Selected
Minimum PIO transfer cycle time without flow control Minimum PIO transfer cycle time with IORDY flow control
Time required for Security erase unit completion Time required for Enhanced security erase unit completion Current Advanced power management value Master Password Revision Code Data Field Type Information
CF Advanced True IDE Timing Mode Capability and Setting Reserved Reserved Reserved

READ DMA (C8h)

Read data from sectors during Ultra DMA and Multiword DMA transfer. Use the SET FEATURES command to specify the mode value. A sector count of zero requests 256 sectors.

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READ MULTIPLE (C4h)
This command performs similarly to the Read Sectors command. Interrupts are not generated on each sector, but on the transfer of a block which contains the number of sectors defined by a Set Multiple command.

READ SECTOR(S) (20h)

This command reads 1 to 256 sectors as specified in the Sector Count register from sectors which is set by Sector number register. A sector count of 0 requests 256 sectors. The transfer beings specified in the Sector Number register.
READ VERIFY SECTOR(S) (40h/41h)
This command verifies one or more sectors on the drive by transferring data from the flash media to the data buffer in the drive and verifying that the ECC is correct. This command is identical to the Read Sectors command, except that DRQ is never set and no data is transferred to the host.

SET FEATURES (EFh)

This command set parameter to Features register and set drives operation. For transfer mode, parameter is set to Sector Count register. This command is used by the host to establish or select certain features.

SET MULTIPLE MODE (C6h)

This command enables the device to perform READ MULTIPLE and WRITE MULTIPLE operations and establishes the block count for these commands.

WRITE DMA (CAh)

Write data to sectors during Ultra DMA and Multiword DMA transfer. Use the SET FEATURES command to specify the mode value.

WRITE MULTIPLE (C5h)

This command is similar to the Write Sectors command. Interrupts are not presented on each sector, but on the transfer of a block which contains the number of sectors defined by Set Multiple command.

WRITE SECTOR(S) (30h)

Write data to a specified number of sectors (1 to 256, as specified with the Sector Count register) from the specified address. Specify 00h to write 256 sectors.

NOP (00h)

The device shall respond with command aborted. For devices implementing the Overlapped feature set, subcommand code 00h in the Features register shall abort any outstanding queue. Subcommand codes 01h through FFh in the Features register shall not affect the status of any outstanding queue.

READ BUFFER (E4h)

The READ BUFFER command enables the host to read a 512-byte block of data.

WRITE BUFFER (E8h)

This command enables the host to write the contents of one 512-byte block of data to the devices buffer.
CHECK POWER MODE (E5h or 98h)
The host can use this command to determine the current power management mode.

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IDLE (E3h or 97h)
This command causes the device to set BSY, enter the Idle mode, clear BSY and generate an interrupt. If sector count is non-zero, the automatic power down mode is enabled. If the sector count is zero, the automatic power mode is disabled.

IDLE IMMEDIATE (E1h or 95h)
This command causes the device to set BSY, enter the Idle(Read) mode, clear BSY and generate an interrupt.

SLEEP (E6h or 99h)

This command causes the device to set BSY, enter the Sleep mode, clear BSY and generate an interrupt.

STANDBY (E2h or 96h)

This command causes the device to set BSY, enter the Sleep mode (which corresponds to the ATA Standby Mode), clear BSY and return the interrupt immediately.
STANDBY IMMEDIATE (E0h or 94h)
This command causes the drive to set BSY, enter the Sleep mode (which corresponds to the ATA Standby Mode), clear BSY and return the interrupt immediately.
SECURITY SET PASSWORD (F1h)
This command set user password or master password. The host outputs sector data with PIO data-out protocol to indicate the information defined in the following table.
Security set Password data content
Word 0 Control word Bit 0 Identifier 0=set user password 1=set master password Bits 1-7 Bit 8 Reserved Security level 0=High 1=Maximum Bits 9-15 1-16 17-255 Reserved Content
Password (32 bytes) Reserved

SECURITY UNLOCK (F2h)

This command disables LOCKED MODE of the device. This command transfers 512 bytes of data from the host with PIO data-out protocol. The following table defines the content of this information.
Security Unlock information Transcend Information Inc.

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Word 0 Control word Bit 0 Identifier Content
0=compare user password 1=compare master password

Bits 1-15 1-16 17-255

Reserved
SECURITY DISABLE PASSWORD (F6h)
Disables any previously set user password and cancels the lock. The host transfers 512 bytes of data, as shown in the following table, to the drive. The transferred data contains a user or master password, which the drive compares with the saved password. If they match, the drive cancels the lock. The master password is still saved. It is re-enabled by issuing the SECURITY SET PASSWORD command to re-set a user password.
SECURITY ERASE PREPARE (F3h)
This command shall be issued immediately before the Security Erase Unit command to enable erasing and unlocking. This command prevents accidental loss of data on the drive.

SECURITY ERASE UNIT (F4h)
The host uses this command to transfer 512 bytes of data, as shown in the following table, to the drive. The transferred data contains a user or master password, which the drive compares with the saved password. If they match, the drive deletes user data, disables the user password, and cancels the lock. The master password is still saved. It is re-enabled by issuing the SECURITY SET PASSWORD command to re-set a user password.
SECURITY FREEZE LOCK (F5h)
Causes the drive to enter Frozen mode. Once this command has been executed, the following commands to update a lock result in the Aborted Command error: SECURITY SET PASSWORD SECURITY UNLOCK SECURITY DISABLE PASSWORD SECURITY ERASE PREPARE SECURITY ERASE UNIT The drive exits from Frozen mode upon a power-off or hard reset. If the SECURITY FREEZE LOCK command is issued when the drive is placed in Frozen mode, the drive executes the command, staying in Frozen mode.

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register. Table shows these Feature register values.
Transcend IDE SSD supports the SMART command set and define some vendor-specific data to report spare/bad block numbers in each memory management unit. Individual SMART commands are identified by the value placed in the Feature
Command Value D0h SMART READ DATA D2h SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE D4h SMART EXECUTE OFF-LINE IMMEDIATE D8h SMART ENABLE OPERATIONS D9h SMART DISABLE OPERATIONS DAh SMART RETURN STATUS

SMART DISABLE OPERATIONS

B0h with a Feature register value of D9h.Disables the SMART function. Upon receiving the command, the drive disables all SMART operations. This setting is maintained when the power is turned off and then back on. Once this command has been received, all SMART commands other than SMART ENABLE OPERATIONS are aborted with the Aborted Command error. This command disables all SMART capabilities including any and all timer and event count functions related exclusively to this feature. After command acceptance, this controller will disable all SMART operations. SMART data in no longer be monitored or saved. The state of SMART is preserved across power cycles.
SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE
B0h with a Feature register value of D2h.Enables or disables the attribute value autosave function. This command specifies whether the current attribute values are automatically saved to the drive when it changes the mode. This setting is maintained when the power is turned on and off.

SMART ENABL OPERATIONS

B0h with a Feature register value of D8h.Enables the SMART function. This setting is maintained when the power is turned off and then back on. Once the SMART function is enabled, subsequent SMART ENABLE OPERATIONS commands do not affect any parameters
SMART EXECUTE OFF-LINE IMMEDIATE

B0h with the content of the Features register equal to D4h. This command causes the device to immediately initiate the optional set of activities that collect SMART data in an off-line mode and then save this data to the device's non-volatile memory, or execute a self-diagnostic test routine in either captive or off-line mode.

SMART RETURN STATUS

B0h with a Feature register value of DAh. This command causes the device to communicate the reliability status of the device to the host. If a threshold exceeded condition is not detected by the device, the device shall set the LBA Mid register

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LBA Mid register to F4h and the LBA High register to 2Ch.
to 4Fh and the LBA High register to C2h. If a threshold exceeded condition is detected by the device, the device shall set the

SMART Read Data

B0h with the content of the Features register is equal to D0h. This command returns the Device SMART data structure to the host. SMART DATA Structure The following 512 bytes make up the device SMART data structure. Users can obtain the data using the

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The above technical information is based on industry standard data and has been tested to be reliable. However, Transcend makes no warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make changes to the specifications at any time without prior notice
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