PC SDRAM Unbuffered DIMM Specification PC SDRAM Specification
PC Serial Presence Detect (SPD) Specification
SFX/SFX12V Power Supply Design Guide System Management BIOS

SMBIOS

Universal Host Controller Interface Design Guide Universal Serial Bus Specification
http://www.usb.org/ developers http://www.usb.org/ developers
Wired for Management Baseline
http://developer.intel.com/ ial/WfM/wfmspecs.htm

1.6 Processor

Use only the processors listed below. Use of unsupported processors can damage the board, the processor, and the power supply. See the Intel Desktop Board D845HV/D845WN Specification Update for the most up-to-date list of supported processors for these boards. The D845HV and D845WN boards support a single Pentium 4 processor (in an mPGA478 socket) with a system bus of 400 MHz. The D845HV and D845WN boards support the processors listed in Table 5. All supported onboard memory can be cached, up to the cachability limit of the processor. See the processors data sheet for cachability limits.

Table 5.

Type Pentium 4 processor

Supported Processors

Designation 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, and 2.0 GHz System Bus 400 MHz L2 Cache Size 256 KB
Use only ATX12V- or SFX12V-compliant power supplies with the D845HV and D845WN boards. ATX12V and SFX12V power supplies have an additional power lead that provides required supplemental power for the Intel Pentium 4 processor. Always connect the 20-pin and 4-pin leads of ATX12V and SFX12V power supplies to the corresponding connectors on the D845HV and D845WN boards, otherwise the board will not boot. Do not use a standard ATX power supply. The board will not boot with a standard ATX power supply.
For information about Processor support Processor usage Power supply connectors
Refer to Section 1.3, page 17 Section 1.3, page 17 Section 2.8.2.3, page 58

1.7 System Memory

Before installing or removing memory, make sure that AC power is disconnected by unplugging the power cord from the computer. Failure to do so could damage the memory and the board.
Remove the AGP video card before installing or upgrading memory to avoid interference with the memory retention mechanism.
The D845HV/D845WN boards have been designed to support DIMMs based on 512 Mbit technology for a maximum onboard capacity of up to 3 GB, but this technology has not been validated on this board. Please refer to the following Intel web sites for the latest lists of tested memory. For the D845HV board: http://developer.intel.com/design/motherbd/hv/hv_mem.htm For the D845WN board: http://developer.intel.com/design/motherbd/wn/wn_mem.htm
To be fully compliant with all applicable Intel SDRAM memory specifications, the board should be populated with DIMMs that support the Serial Presence Detect (SPD) data structure. This allows the BIOS to read the SPD data and program the chipset to accurately configure memory settings for optimum performance. If non-SPD memory is installed, the BIOS will attempt to correctly configure the memory settings, but performance and reliability may be impacted or the DIMMs may not function under the determined frequency. The D845HV and D845WN boards both have three DIMM sockets and support the following memory features: 3.3 V (only) 168-pin SDRAM DIMMs with gold-plated contacts Unbuffered single-sided or double-sided DIMMs Maximum total system memory: 3 GB; minimum total system memory: 32 MB 133 MHz SDRAM DIMMs only Serial Presence Detect (SPD) Suspend to RAM Non-ECC and ECC DIMMs

For information about The location of the front panel connector The signal names of the infrared port on the front panel connector The IrDA specification Refer to Figure 15, page 68 Table 45, page 70 Section 1.5, page 18

Parallel Port

The 25-pin D-Sub parallel port connector is located on the back panel. In the BIOS Setup program, the parallel port can be set to the following modes: Output only (PC AT-compatible mode) Bi-directional (PS/2 compatible) EPP ECP
Refer to Figure 10, page 52 Table 20, page 53 Table 66, page 102
For information about The location of the parallel port connector The signal names of the parallel port connector Setting the parallel ports mode
Diskette Drive Controller
The I/O controller supports one diskette drive that is compatible with the 82077 diskette drive controller and supports both PC-AT and PS/2 modes.
For information about The location of the diskette drive connector The signal names of the diskette drive connector The supported diskette drive capacities and sizes Refer to Figure 13, page 61 Table 38, page 66 Table 69, page 107
Keyboard and Mouse Interface
PS/2 keyboard and mouse connectors are located on the back panel. The +5 V lines to these connectors are protected with a PolySwitch circuit that, like a self-healing fuse, reestablishes the connection after an overcurrent condition is removed.
The keyboard is supported in the bottom PS/2 connector and the mouse is supported in the top PS/2 connector. Power to the computer should be turned off before a keyboard or mouse is connected or disconnected. The keyboard controller contains the AMI keyboard and mouse controller code, provides the keyboard and mouse control functions, and supports password protection for power-on/reset. A power-on/reset password can be specified in the BIOS Setup program.
For information about The location of the keyboard and mouse connectors The signal names of the keyboard and mouse connectors Refer to Figure 10, page 52 Table 18, page 53

I/O Controller Option

1.10 Audio Subsystem (Optional)
The optional audio subsystem includes these features: Split digital/analog architecture for improved S/N (signal-to-noise) ratio: 85 dB Power management support for ACPI 1.0 (driver dependant) 3-D stereo enhancement Mic in pre-amp that supports dynamic, condenser, and electret microphones ATAPI-style connectors: Telephony Auxiliary line in CD-ROM Front panel audio connector, including pins for: Line out Mic in Back panel audio connectors: Line out Line in Mic in The audio subsystem consists of the following devices: Intel 82801BA I/O Controller Hub (ICH2) Analog Devices AD1885 audio codec

Technical Reference

Table 13.

I/O Map (continued)

Description ICH2 (ACPI + TCO) D845HV/D845WN board resource Onboard audio controller ICH2 (USB controller #1) ICH2 (SMBus) Intel 82801BA PCI bridge ICH2 audio mixer ICH2 audio bus mixer ICH2 modem mixer ICH2 (USB controller #2) LPC47M142
Address (hex) 96 contiguous bytes starting on a 128-byte divisible boundary 64 contiguous bytes starting on a 64-byte divisible boundary 64 contiguous bytes starting on a 64-byte divisible boundary 32 contiguous bytes starting on a 32-byte divisible boundary 16 contiguous bytes starting on a 16-byte divisible boundary 4096 contiguous bytes starting on a 4096-byte divisible boundary 256 contiguous bytes starting on a 256-byte divisible boundary 64 contiguous bytes starting on a 64-byte divisible boundary 256 contiguous bytes starting on a 256-byte divisible boundary 32 contiguous bytes starting on a 32-byte divisible boundary 96 contiguous bytes starting on a 128-byte divisible boundary
* ** *** Dword access only. Byte access only.
Default, but can be changed to another address range.
Some additional I/O addresses are not available due to ICH2 address aliassing.
For information about ICH2 addressing Refer to Section 1.3 on page 17

2.4 DMA Channels

Table 14.

DMA Channels

Data Width 8 or 16 bits 8 or 16 bits 8 or 16 bits 8 or 16-bits 8 or 16 bits 16 bits 16 bits 16 bits System Resource Open Parallel port Diskette drive Parallel port (for ECP or EPP) DMA controller Open Open Open

DMA Channel Number

2.5 PCI Configuration Space Map
Table 15. PCI Configuration Space Map
Device Number (hex) 1E 1F 1F 1F 1F 1F 1F 1F 09 0A 0B 0C 0D 0E

D845WN board only.

Bus Number (hex) 02 02
Function Number (hex) 00 00
Description Memory controller of Intel 82845 component PCI to AGP bridge Hub link to PCI bridge Intel 82801BA ICH2 PCI to LPC bridge IDE controller USB SMBus controller USB AC 97 audio controller (optional) AC 97 modem controller (optional) Add-in AGP adapter card LAN controller (optional) PCI bus connector 1 PCI bus connector 2 PCI bus connector 3 PCI bus connector 4 (Note) PCI bus connector 5 (Note) PCI bus connector 6 (Note)

2.6 Interrupts

Table 16.

IRQ NMI 14 15

Interrupts
System Resource I/O channel check Reserved, interval timer Reserved, keyboard buffer full Reserved, cascade interrupt from slave PIC COM2 (Note) COM1 (Note) LPT2 (Plug and Play option) / Audio / User available Diskette drive LPT1 (Note) Real-time clock Reserved for ICH2 system management bus User available User available Onboard mouse port (if present, else user available) Reserved, math coprocessor Primary IDE (if present, else user available) Secondary IDE (if present, else user available)

(Note) (Note) (Note)

PIRQB INTB INTB
Other INTA to PIRQA INTD to PIRQD INTC to PIRQH
INTB INTA to PIRQE INTA INTD INTC INTB INTA INTB INTB INTA INTD INTC INTB INTC INTC INTB INTA INTD INTC INTD INTD INTC INTB INTA INTD INTA
The ICH2 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal.

2.8 Connectors

Only the back panel, the front panel audio, and the front panel USB connectors of the D845HV and D845WN boards have overcurrent protection. The D845HV and D845WN boards internal connectors are not overcurrent protected and should connect only to devices inside the computers chassis, such as fans and internal peripherals. Do not use these connectors to power devices external to the computers chassis. A fault in the load presented by the external devices could cause damage to the computer, the interconnecting cable, and the external devices themselves. This section describes the boards connectors. The connectors can be divided into the following groups: Back panel I/O connectors (see page 52) PS/2 keyboard and mouse USB Parallel port Serial port A LAN Audio (Line out, Line in, and Mic in) Internal I/O connectors (see page 55) Audio (telephony, auxiliary line input, and ATAPI CD-ROM) Fans Power Add-in boards (CNR, PCI, and AGP) IDE Diskette drive SCSI LED External I/O connectors (see page 68) Front panel audio Front panel USB Serial port B Auxiliary front panel power/sleep/message-waiting LED Front panel (power/sleep/message-waiting LED, power switch, hard drive activity LED, reset switch, and auxiliary front panel power LED)
When installing the board in a microATX chassis, make sure that peripheral devices are installed at least 1.5 inches above the main power connector, the diskette drive connector, the IDE connector, and the DIMM sockets.

Back Panel Connectors

Figure 10 shows the location of the back panel connectors. The back panel connectors are color-coded in compliance with PC 99 recommendations. The figure legend below lists the colors used.
Item A B C D E F G H I J K L Description PS/2 mouse port PS/2 keyboard port USB port (optional) USB port (optional) Serial port A Parallel port LAN (optional) USB port USB port Mic in (optional)
Color Green Purple Black Black Teal

OM11429

For more information see: Table 18 Table 18 Table 19 Table 19 Table 21 Table 20 Table 22 Table 19 Table 19 Table 25 Table 24 Table 23
Burgundy Black Black Black Pink Lime green Light blue
Audio line out (optional) Audio line in (optional)
Figure 10. Back Panel Connectors
The back panel audio line out connector is designed to power headphones or amplified speakers only. Poor audio quality occurs if passive (non-amplified) speakers are connected to this output.

2.8.2.2

Audio Connectors (Optional)
Figure 11 shows the location of the audio connectors.

OM11430

Item A B C
Description Telephony (optional) Auxiliary line in, ATAPI style (optional) ATAPI CD-ROM (optional)

Color Green White Black

For more information see: Table 26 Table 27 Table 28
Figure 11. Audio Connectors
The front panel audio connector is described in Section 2.8.3, beginning on page 68.

Table 26.

Telephony Connector (Optional)
Signal Name Audio_Mono_In Ground Ground Audio_Mono_Out

Table 27.

Auxiliary Line In Connector (Optional)
Signal Name Left auxiliary line in Ground Ground Right auxiliary line in

Table 28.

ATAPI CD-ROM Connector (Optional)
Signal Name Left audio input from CD-ROM CD audio differential ground CD audio differential ground Right audio input from CD-ROM

2.8.2.3

Power and Hardware Control Connectors
Figure 12 shows the location of the power and hardware control connectors.

Item A B C D E F

OM11431
Description ATX12V power Rear chassis fan Processor fan Main power Chassis intrusion Front chassis fan (optional)
For more information see: Table 29 Table 30 Table 31 Table 32 Table 33 Table 34
Figure 12. Power and Hardware Control Connectors
For information about The power connector The functions of the fan connectors
Refer to Section 1.14.2.1, page 41 Section 1.14.2.2, page 42

Table 29.

Pin 1 2

ATX12V Power Connector

Signal Name Ground Ground Pin Signal Name +12 V +12 V
The board will not boot if the ATX12V power connector is not attached to the board.

Table 30.

Rear Chassis Fan Connector
Signal Name Ground VREG_12V_POWER REAR_FAN_TACH

Table 31.

Processor Fan Connector
Signal Name Ground VREG_12V_POWER FAN_TACH

Table 32.

Pin 9 10

Main Power Connector

Signal Name +3.3 V +3.3 V Ground +5 V Ground +5 V Ground PWRGD (Power Good) +5 V (Standby) +12 V Pin Signal Name +3.3 V -12 V Ground PS-ON# (power supply remote on/off) Ground Ground Ground No connect +5 V +5 V

Table 33.

Chassis Intrusion Connector
Signal Name Intruder Ground

Table 34.

Front Chassis Fan Connector (Optional)
Signal Name Ground +12 V No connect

2.8.2.4

Add-in Board and Peripheral Interface Connectors
Figure 13 shows the location of the add-in board connector and peripheral connectors for the D845HV board. Note the following considerations for the PCI bus connectors (for both boards): All of the PCI bus connectors are bus master capable. PCI bus connector 1 has SMBus signals routed to it. This enables PCI bus add-in boards with SMBus support to access sensor data on the board. The specific SMBus signals are as follows: The SMBus clock line is connected to pin A40 The SMBus data line is connected to pin A41

A B C D E

OM11432

Item A B C D E F G H I

Description Communication and networking riser (CNR) PCI bus connector 3 PCI bus connector 2 PCI bus connector 1 AGP connector Diskette drive Primary IDE Secondary IDE SCSI LED (Optional)
For more information see: Table 35 Table 36 Table 36 Table 36 Table 37 Table 38 Table 39 Table 39 Table 40
Figure 13. D845HV Add-in Board and Peripheral Interface Connectors
Figure 14 shows the location of the add-in board connector and peripheral connectors for the D845WN board.

A B C D E F G H

Item A B C D E F G H I J K L Description

OM11433

For more information see: Table 35 Table 36 Table 36 Table 36 Table 36 Table 36 Table 36 Table 37 Table 38 Table 39 Table 39 Table 40
Communication and networking riser (CNR) PCI bus connector 6 PCI bus connector 5 PCI bus connector 4 PCI bus connector 3 PCI bus connector 2 PCI bus connector 1 AGP connector Diskette drive Primary IDE Secondary IDE SCSI LED (Optional)
Figure 14. D845WN Add-in Board and Peripheral Interface Connectors

Table 35.

Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30
Pin B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 Signal Name Reserved Reserved Reserved Ground Reserved Reserved Ground LAN_TXD1 LAN_RSTSYNC Ground LAN_RXD2 LAN_RXD0 Ground Reserved +5 V (dual) USB_OC Ground -12 V +3.3 V Ground EED0 EECK Ground SMB_A0 SMB_SCL CDC_DWN_ENAB Ground AC97_SYNC AC97_SDATA_OUT AC97_BITCLK
Signal Name Reserved Reserved Ground Reserved Reserved Ground LAN_TXD2 LAN_TXD0 Ground LAN_CLK LAN_RXD1 Reserved USB+ Ground USB+12 V Ground +3.3 V (dual) +5 V Ground EEDI EECS SMB_A1 SMB_A2 SMB_SDA AC97_RESET Reserved AC97_SDATA_IN1 AC97_SDATA_IN0 Ground
For information about The CNR
Refer to Section 1.12, page 35

Table 36.

Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31

* ** ***

PCI Bus Connectors

For information about IDE Configuration Submenu in the BIOS Setup program Refer to Section 4.4.4, page 104
3.10 BIOS Security Features
The BIOS includes security features that restrict access to the BIOS Setup program and who can boot the computer. A supervisor password and a user password can be set for the BIOS Setup program and for booting the computer, with the following restrictions: The supervisor password gives unrestricted access to view and change all the Setup options in the BIOS Setup program. This is the supervisor mode. The user password gives restricted access to view and change Setup options in the BIOS Setup program. This is the user mode. If only the supervisor password is set, pressing the <Enter> key at the password prompt of the BIOS Setup program allows the user restricted access to Setup. If both the supervisor and user passwords are set, users can enter either the supervisor password or the user password to access Setup. Users have access to Setup respective to which password is entered. Setting the user password restricts who can boot the computer. The password prompt will be displayed before the computer is booted. If only the supervisor password is set, the computer boots without asking for a password. If both passwords are set, the user can enter either password to boot the computer.
Table 57 shows the effects of setting the supervisor password and user password. This table is for reference only and is not displayed on the screen.
Table 57. Supervisor and User Password Functions
User Mode Setup Options Password to Enter Setup None Supervisor Password During Boot None None
Supervisor Password Set Mode Neither Supervisor only User only Supervisor and user set
Can change all options (Note) Can change all options N/A Can change all options
Can change all None options (Note) Can change a limited number of options Supervisor Password
Can change all Enter Password options Clear User Password Can change a limited number of options Supervisor Password Enter Password

User Supervisor or user

If no password is set, any user can change all Setup options.
For information about Setting user and supervisor passwords

The menu shown in Table 60 is for clearing Setup passwords and enabling extended configuration mode. Setup only displays this menu in configuration mode. See Section 2.9 on page 72 for configuration mode setting information.

Table 60.

Feature Clear All Passwords

Maintenance Menu

Options Yes (default) No Description Clears the user and supervisor passwords. Clears the Wired for Management Boot Integrity Service (BIS) credentials. Invokes the Extended Configuration submenu. Displays CPU Information. Displays CPUs Stepping Signature. Displays CPUs Microcode Update Revision.
Clear BIS Credentials Yes (default) No Extended Configuration CPU Information CPU Stepping Signature CPU Microcode Update Revision Default (default) User-Defined No options No options No options

BIOS Setup Program

Extended Configuration Submenu
To access this submenu, select Maintenance on the menu bar and then Extended Configuration.
The submenu represented by Table 61 is for setting video memory cache mode. This submenu becomes available when User Defined is selected under Extended Configuration.

Table 61.

Feature Extended Configuration
Options Default (default) User Defined USWC Description User Defined allows setting memory control and video memory cache mode. If selected here, will also display in the Advanced Menu as: Extended Menu: Used. Selects Uncacheable Speculative Write-Combining (USWC) video memory cache mode. Full 32 byte contents of the Write Combining buffer are written to memory as required. Cache lookups are not performed. Both the video driver and the application must support Write Combining. Selects UnCacheable (UC) video memory cache mode. This setting identifies the video memory range as uncacheable by the processor. Memory writes are performed in program order. Cache lookups are not performed. Well suited for applications not supporting Write Combining. Sets extended memory configuration options to Auto or User Defined. Selects the number of clock cycles required to address a column in memory.

Video Memory Cache Mode

UC (default)

SDRAM Auto-Configuration

Auto (default) User Defined Auto (default)

CAS# Latency

SDRAM RAS# to CAS# Delay

Auto (default)

Selects the number of clock cycles between addressing a row and addressing a column.

SDRAM RAS# Precharge

Selects the length of time required before accessing a new row.
SDRAM RAS# Active to Precharge

5 Auto (default)

Corresponds to tRAS.

4.3 Main Menu

To access this menu, select Main on the menu bar at the top of the screen.

Table 62 describes the Main menu. This menu reports processor and memory information and is for configuring the system date and system time.

Table 62.

Feature BIOS Version Processor Type Processor Speed System Bus Speed Cache RAM Total Memory Memory Bank 0 Memory Bank 1 Memory Bank 2 Language

Main Menu

Options No options No options No options No options No options No options No options Description Displays the version of the BIOS. Displays processor type. Displays processor speed. Displays the system bus speed. Displays the size of second-level cache and whether it is ECC-capable. Displays the total amount of RAM. Displays the amount and type of RAM in the memory banks. Selects the current default language used by the BIOS.
English (default) Espaol Deutsch Italiano Franais

Memory Configuration

Non-ECC ECC (default)
Allows the user to enable error reporting if the system and all installed memory support ECC. If non-ECC memory is installed, BIOS will detect and change the setting to Non-ECC. Specifies the current time. Specifies the current date.

System Time System Date

Hour, minute, and second Day of week Month/day/year

4.4 Advanced Menu

To access this menu, select Advanced on the menu bar at the top of the screen.
PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration
Table 63 describes the Advanced Menu. This menu is used for setting advanced features that are available through the chipset.

Table 63.

Feature Extended Configuration PCI Configuration Boot Configuration Peripheral Configuration IDE Configuration Diskette Configuration Event Log Configuration Video Configuration

Advanced Menu

Options No options Select to display submenu Select to display submenu Select to display submenu Select to display submenu Select to display submenu Select to display submenu Select to display submenu Description If Used is displayed, User-Defined has been selected in Extended Configuration under the Maintenance Menu. Configures individual PCI slots IRQ priority. Configures Plug and Play and the Numlock key, and resets configuration data. Configures peripheral ports and devices. Specifies type of connected IDE devices. Configures the diskette drive. Configures Event Logging. Configures video features.

The submenu represented in Table 74 is for setting the ACPI power options.

Table 74.

Feature ACPI Suspend State Wake on LAN from S5
Options S1 State (default) S3 State Stay Off (default) Power On In ACPI soft-off mode only, determines how the system responds to a LAN wake-up event. Description Specifies the ACPI sleep state.

4.7 Boot Menu

To access this menu, select Boot from the menu bar at the top of the screen.
Boot Device Priority Hard Disk Drives Removable Devices ATAPI CD-ROM Drives
The menu represented in Table 75 is used to set the boot features and the boot sequence.

Table 75.

Feature Quiet Boot

Boot Menu

Options Disabled Enabled (default) Description
Disabled displays normal POST messages. Enabled displays OEM graphic instead of POST messages.
Enables the computer to boot without running certain POST tests. Enables the BIOS to scan the flash memory for user binary files that are executed at boot time. Specifies the boot sequence from the available types of boot devices. Specifies the boot sequence from the available hard disk drives. Specifies the boot sequence from the available removable devices. Specifies the boot sequence from the available ATAPI CD-ROM drives.

Scan User Flash Area

Disabled (default) Enabled Select to display submenu Select to display submenu Select to display submenu Select to display submenu
Boot Device Priority Submenu
To access this menu, select Boot on the menu bar and then Boot Devices Priority.
The submenu represented in Table 76 is for setting boot devices priority.

Table 76.

Feature 1 Boot Device 2 Boot Device 3 Boot Device 4 Boot Device

th rd nd st

Options Removable Dev. Hard Drive ATAPI CD-ROM Intel Boot Agent Disabled Description Specifies the boot sequence according to the device type. The computer will attempt to boot from up to five devices as specified here. Only one of the devices can be an IDE hard disk drive. To specify boot sequence: 1. 2. Select the boot device with <> or <>. Press <Enter> to set the selection as the intended boot device.
The default settings for the first through fourth boot devices are, respectively: Removable Dev. Hard Drive ATAPI CD-ROM Intel Boot Agent

Hard Disk Drives Submenu

To access this menu, select Boot on the menu bar and then Hard Disk Drives.
The submenu represented in Table 77 is for setting hard disk drive priority.

Discard Changes

5.1 5.2 5.3 5.4 5.5 BIOS Error Messages....119 Port 80h POST Codes....121 Bus Initialization Checkpoints...125 Speaker (Optional)....126 BIOS Beep Codes....126

5.1 BIOS Error Messages

Table 81 lists the error messages and provides a brief description of each.

Table 81.

GA20 Error Pri Master HDD Error Pri Slave HDD Error Sec Master HDD Error Sec Slave HDD Error Pri Master Drive - ATAPI Incompatible Pri Slave Drive - ATAPI Incompatible Sec Master Drive - ATAPI Incompatible Sec Slave Drive - ATAPI Incompatible A: Drive Error Cache Memory Bad CMOS Battery Low CMOS Display Type Wrong CMOS Checksum Bad CMOS Settings Wrong CMOS Date/Time Not Set DMA Error FDC Failure HDC Failure

BIOS Error Messages

Explanation An error occurred with Gate A20 when switching to protected mode during the memory test. Could not read sector from corresponding drive.

Error Message

Corresponding drive in not an ATAPI device. Run Setup to make sure device is selected correctly.
No response from diskette drive. An error occurred when testing L2 cache. Cache memory may be bad. The battery may be losing power. Replace the battery soon. The display type is different than what has been stored in CMOS. Check Setup to make sure type is correct. The CMOS checksum is incorrect. CMOS memory may have been corrupted. Run Setup to reset values. CMOS values are not the same as the last boot. These values have either been corrupted or the battery has failed. The time and/or date values stored in CMOS are invalid. Run Setup to set correct values. Error during read/write test of DMA controller. Error occurred trying to access diskette drive controller. Error occurred trying to access hard disk controller. continued
BIOS Error Messages (continued)
Explanation NVRAM is being checked to see if it is valid. NVRAM was invalid and has been updated. NVRAM was invalid but was unable to be updated. Error in the keyboard connection. Make sure keyboard is connected properly. Keyboard interface test failed. Memory size has decreased since the last boot. If no memory was removed then memory may be bad. Memory size has increased since the last boot. If no memory was added there may be a problem with the system. Memory size has changed since the last boot. If no memory was added or removed then memory may be bad. System did not find a device to boot. A parity error occurred on an off-board card. This error is followed by an address. A parity error occurred in onboard memory. This error is followed by an address. A parity error occurred in onboard memory at an unknown address. NVRAM, CMOS, and passwords have been cleared. The system should be powered down and the jumper removed. CMOS is ignored and NVRAM is cleared. User must enter Setup.

E8 E9 EA EB EC EF

Table 84.
Code 08 0B 0C 0E 0F 1A 28 2A 2B 2C 2D 2E 2F 39 3A
Runtime Code Uncompressed in F000 Shadow RAM
Description of POST Operation NMI is Disabled. To check soft reset/power-on. BIOS stack set. Going to disable cache if any. POST code to be uncompressed. CPU init and CPU data area init to be done. CMOS checksum calculation to be done next. Any initialization before keyboard BAT to be done next. KB controller I/B free. To issue the BAT command to keyboard controller. Any initialization after KB controller BAT to be done next. Keyboard command byte to be written. Going to issue Pin-23,24 blocking/unblocking command. Going to check pressing of <INS>, <END> key during power-on. To init CMOS if "Init CMOS in every boot" is set or <END> key is pressed. Going to disable DMA and Interrupt controllers. Video display is disabled and port-B is initialized. Chipset init about to begin. 8254 timer test about to start. About to start memory refresh test. Memory Refresh line is toggling. Going to check 15 s ON/OFF time. To read 8042 input port and disable Megakey GreenPC feature. Make BIOS code segment writeable. To do any setup before Int vector init. Interrupt vector initialization to begin. To clear password if necessary. Any initialization before setting video mode to be done. Going for monochrome mode and color mode setting. Different buses init (system, static, output devices) to start if present. (See Section 5.3 for details of different buses.) To give control for any setup required before optional video ROM check. To look for optional video ROM and give control. To give control to do any processing after video ROM returns control. If EGA/VGA not found then do display memory R/W test. EGA/VGA not found. Display memory R/W test about to begin. Display memory R/W test passed. About to look for the retrace checking. Display memory R/W test or retrace checking failed. To do alternate Display memory R/W test. Alternate Display memory R/W test passed. To look for the alternate display retrace checking. Video display checking over. Display mode to be set next. Display mode set. Going to display the power-on message. Different buses init (input, IPL, general devices) to start if present. (See Section 5.3 for details of different buses.) Display different buses initialization error messages. (See Section 5.3 for details of different buses.) New cursor position read and saved. To display the Hit <DEL> message. continued
Code 49 4B 4C 4D 4E 4F 7F 82 83
Runtime Code Uncompressed in F000 Shadow RAM (continued)
Description of POST Operation To prepare the descriptor tables. To enter in virtual mode for memory test. To enable interrupts for diagnostics mode. To initialize data to check memory wrap around at 0:0. Data initialized. Going to check for memory wrap around at 0:0 and finding the total system memory size. Memory wrap around test done. Memory size calculation over. About to go for writing patterns to test memory. Pattern to be tested written in extended memory. Going to write patterns in base 640k memory. Patterns written in base memory. Going to find out amount of memory below 1M memory. Amount of memory below 1M found and verified. Going to find out amount of memory above 1M memory. Amount of memory above 1M found and verified. Check for soft reset and going to clear memory below 1M for soft reset. (If power on, go to check point # 4Eh). Memory below 1M cleared. (SOFT RESET) Going to clear memory above 1M. Memory above 1M cleared. (SOFT RESET) Going to save the memory size. (Go to check point # 52h). Memory test started. (NOT SOFT RESET) About to display the first 64k memory size. Memory size display started. This will be updated during memory test. Going for sequential and random memory test. Memory testing/initialization below 1M complete. Going to adjust displayed memory size for relocation/ shadow. Memory size display adjusted due to relocation/ shadow. Memory test above 1M to follow. Memory testing/initialization above 1M complete. Going to save memory size information. Memory size information is saved. CPU registers are saved. Going to enter in real mode. Shutdown successful, CPU in real mode. Going to disable gate A20 line and disable parity/NMI. A20 address line, parity/NMI disable successful. Going to adjust memory size depending on relocation/shadow. Memory size adjusted for relocation/shadow. Going to clear Hit <DEL> message. Hit <DEL> message cleared. <WAIT.> message displayed. About to start DMA and interrupt controller test. DMA page register test passed. To do DMA#1 base register test. DMA#1 base register test passed. To do DMA#2 base register test. DMA#2 base register test passed. To program DMA unit 1 and 2. DMA unit 1 and 2 programming over. To initialize 8259 interrupt controller. Extended NMI sources enabling is in progress. Keyboard test started. Clearing output buffer, checking for stuck key, to issue keyboard reset command. Keyboard reset error/stuck key found. To issue keyboard controller interface test command. Keyboard controller interface test over. To write command byte and init circular buffer. Command byte written, global data init done. To check for lock-key. continued

Code AE B1 00

Description of POST Operation Uncompress SMBIOS module and init SMBIOS code and form the runtime SMBIOS image in shadow. Going to copy any code to specific area. Copying of code to specific area done. Going to give control to INT-19 boot loader.
5.3 Bus Initialization Checkpoints
The system BIOS gives control to the different buses at several checkpoints to do various tasks. Table 85 describes the bus initialization checkpoints.

Table 85.

Checkpoint 2A 95
Bus Initialization Checkpoints
Description Different buses init (system, static, and output devices) to start if present. Different buses init (input, IPL, and general devices) to start if present. Display different buses initialization error messages. Init of different buses optional ROMs from C800 to start.
While control is inside the different bus routines, additional checkpoints are output to port 80h as WORD to identify the routines under execution. In these WORD checkpoints, the low byte of the checkpoint is the system BIOS checkpoint from which the control is passed to the different bus routines. The high byte of the checkpoint is the indication of which routine is being executed in the different buses. Table 86 describes the upper nibble of the high byte and indicates the function that is being executed.

Table 86.

Value 6 7
Upper Nibble High Byte Functions
Description func#0, disable all devices on the bus concerned. func#1, static devices init on the bus concerned. func#2, output device init on the bus concerned. func#3, input device init on the bus concerned. func#4, IPL device init on the bus concerned. func#5, general device init on the bus concerned. func#6, error reporting for the bus concerned. func#7, add-on ROM init for all buses.
Table 87 describes the lower nibble of the high byte and indicates the bus on which the routines are being executed.

Table 87.

Value 4 5
Lower Nibble High Byte Functions
Description Generic DIM (Device Initialization Manager) On-board System devices ISA devices EISA devices ISA PnP devices PCI devices

5.4 Speaker (Optional)

A 47 inductive speaker is mounted on the D845HV and the D845WN board. The speaker provides audible error code (beep code) information during POST.
For information about The location of the onboard speaker on the D845HV board The location of the onboard speaker on the D845WN board Refer to Figure 1, page 14 Figure 2, page 15

5.5 BIOS Beep Codes

Whenever a recoverable error occurs during POST, the BIOS displays an error message describing the problem (see Table 88). The BIOS also issues a beep code (one long tone followed by two short tones) during POST if the video configuration fails (a faulty video card or no card installed) or if an external ROM module does not properly checksum to zero. An external ROM module (for example, a video BIOS) can also issue audible errors, usually consisting of one long tone followed by a series of short tones. For more information on the beep codes issued, check the documentation for that external device. There are several POST routines that issue a POST terminal error and shut down the system if they fail. Before shutting down the system, the terminal-error handler issues a beep code signifying the test point error, writes the error to I/O port 80h, attempts to initialize the video and writes the error in the upper left corner of the screen (using both monochrome and color adapters).