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Dual 701

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Dual 701IBM Fan ASSY Dual 701X-H70 RISCWarranty: 30 Day Warranty #93H8868


Details
Brand: IBM
Part Numbers: 93H8868, 93h8868


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Comments to date: 4. Page 1 of 1. Average Rating:
nusntusmu 4:02pm on Tuesday, June 8th, 2010 
Poor quality I purchased this for dictating in an NHS Trust that is too overspent to supply adequate numbers of dictaphones for its consultant staff.
tufan 1:00pm on Tuesday, May 18th, 2010 
Olympus Dictaphone This dictaphone is a simple one and easy to use. My daughter is using it to record her revision notes for her A levels. Reliable, basic workhorse recorder I have had one of these for years and it is still going strong. Recording quality is perfectly acceptable.
arunr110 9:54pm on Friday, April 16th, 2010 
Pearlcorded S701 I am very satisfied with the recorder. I bought it so I could have one and it performs like it is suppose to do.
borft 8:00am on Thursday, March 18th, 2010 
This is a repeat buy. Reasonably priced, this gadget is easy to use and does exactly what it says on the tin.

Comments posted on www.ps2netdrivers.net are solely the views and opinions of the people posting them and do not necessarily reflect the views or opinions of us.

 

Documents

doc0

PD-97578A

Radiation Hardended, 100V, Dual 1.0A, Solid State Relay

Product Summary

Part Number

RDHA701CD10A2NX

Voltage Current Configuration Rad Level

100V 1.0A Dual DC 100K

Description
The RDHA701CD10A2NX is a radiation hardened dual Solid State Relay in a hermatic package. It is configured as dual single pole single throw (SPST) normally open relay. This device is characterized for 100KRad (Si) total ionizing dose. The output MOSFET utilizes International Rectifiers R5 Technology.

Features:

n Total Dose Capability to 100KRad (Si) n Optically Coupled n 1000VDC Input-to-Output, Channel-to-Channel,
and Pin-to-Case Isolation
n Hermetically Sealed Ceramic Package
Absolute Maximum Ratings @ Tj = 25C (unless otherwise specified)

Parameter

Output Current f Output Withstand Voltage

Symbol

VO (OFF) IO IF IF pk VR PDISS TJ TS TL
100 1.100 5.0 1.0 -55 to +125 -65 to +0.8 (typ)

V A mA V W C g

Input Forward Current Peak Input Forward Current (t 1.0ms) Peak Input Reverse Voltage (t 1.0ms) Power Dissipation Operating Temperature Range Storage Temperature Range Lead Temperature (soldering 10sec) Weight
For notes, please refer to page 2

www.irf.com

10/26/10
Electrical Characteristics per Channel @ -55CdTCd+125C (Unless Otherwise Specified)
Output On-Resistance Output Leakage Current Input Forward Voltage Input-to-Output Leakage Current Channel-to-Channel Leakage Current Pin-to-Case Leakage Current Turn-On Time Turn-Off Time

Group A

Subgroups 1, 2, 3 1

Test Conditions

IF = 10mA, IO= 1.0A IF = 0, VOUT = 100V IF = 10mA VI-O = 1000Vdc, dwell = 5s IF = 0 to 10mA, VBus = 28V, IO = 1.0A, Duty Cycle 1.0% IF = 10mA to 0, VBus = 28V, IO = 1.0A, Duty Cycle 1.0% IF= 0, V=+25V, f=1MHz,TC=25C Per Channel MIL-HDBK-217F, SF@ TC=25C
Symbol Min. Typ. Max. Units
RDS(ON) IO VF II-O ICH-CH ICASE --1.0 A ----1.0 0.25 0.39 ---0.40 0.25 1.85 A V

gh gh c c

9, 10, 11 9, 10, 11

ton toff COSS RTHJC

----22.7

--110 ---

4.0 ms 2.0 -15 -pF C/W MHrs
Output Capacitance Thermal Resistance MTBF
Notes for Maximum Ratings and Electrical Characteristic Tables
Specification is guaranteed by design. Rise and fall times are controlled internally. Optically coupled Solid State Relays (SSRs) have relatively slow turn-on and turn-off times. Care must be taken to insure that transient currents do not cause a violation of SOA. If transient conditions are present, IR recommends a complete simulation to be performed by the end user to ensure compliance with SOA requirements as specified in the IRHQ57110 data sheet. m While the SSR design meets the design requirements specified in MIL-PRF-38534, the end user is responsible for product derating, as applicable for the application. n Reference Fig. 2 for Switching Test Circuit and Fig. 3 for Switching Test Wave Form. o Turn-On Time (ton) includes the turn-on delay and rise time; Turn-Off Time (toff) includes the turn-off delay and fall time International Rectifier does not currently have a DLA certified Radiation Hardness Assurance Plan.

Anode V_OUT_1+ 8

Cathode V_OUT_23

V_OUT_17 Cathode 2 6

V_OUT_2+ 4

Anode 2 5

Fig 1: Block Diagram

Anode 1 1

V_OUT_1+ 8

V_OUT_2+ 4 RS

Fig 2: Switching Test Circuit www.irf.com 3

10% 90%

Fig 3: Switching Test Waveform
Case Outline and Dimensions Package (8 Pin Ceramic)
1. 2. 3. 4. Dimensioning and Tolerancing per ASME Y14.5SM-1994 Controlling Dimension: Inch Dimensions are shown in inches Tolerances are +/- 0.005 UOS
Part Numbering Nomenclature

RD H A CD 10 A 2 N X

Device Type RD=DC Solid State Relay Radiation Hardening Blank= No Rad Tolerance H=RAD Hard Generation A=Current design Radiation Level 7=100K Rad (Si) Current 01=1.0A Package CD=8 pin Ceramic

Screening Level P=Unscreened. 25C (Electrical test Not for qualification ) X=Screening per MIL-PRF-38534 Class K is available. (Fully compliant Class K is presently pending DLA Approval.) Features N=Non Buffered Fast Poles 2=2 Poles
Throw Configuration A=Single Throw, normally Open Voltage 10=100 volts
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 IR LEOMINSTER : 205 Crawford St., Leominster, Massachusetts 01453, USA Tel: (978) 534-5776 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. Data and specifications subject to change without notice. 10/2010

doc1

Philips Semiconductors RF Communications Products

Product specification

Divide by: 128/129-64/65 dual modulus low power ECL prescaler

DESCRIPTION

The SA701 is an advanced dual modulus (Divide By 128/129 or 64/65) low power ECL prescaler. The minimum supply voltage is 2.7V and is compatible with the CMOS UMA1005 synthesizer from Philips and other logic circuits. The low supply current allows application in battery operated low-power equipment. Maximum input signal frequency is 1.1GHz for cellular and other land mobile applications. There is no lower frequency limit due to a fully static design. The circuit is implemented in ECL technology on the QUBiC process. The circuit will be available in an 8-pin SO package with 150 mil package width and in 8-pin dual in-line plastic package, and is pin compatible with Fujitsu MB501, Plessey SP8704 and Motorola MC12022.

FEATURES

Low voltage operation Low current consumption Operation up to 1.1GHz ESD hardened

APPLICATIONS

PIN CONFIGURATION

N, D Package

IN nc MC GND
Cellular phones Cordless phones RF LANs Test and measurement Military radio VHF/UHF mobile radio VHF/UHF hand-held radio

ORDERING INFORMATION

DESCRIPTION 8-Pin Plastic Dual In-Line Package (DIP) 8-Pin Plastic Small Outline (SO) package (Surface-mount) TEMPERATURE RANGE -40 to +85C -40 to +85C ORDER CODE SA701N SA701D DWG # 0404B 0174C

ABSOLUTE MAXIMUM RATINGS

SYMBOL VCC VIN IO TSTG TA JA Supply voltage Voltage applied to any other pin Output current Storage temperature range Operating ambient temperature range Thermal impedance D package N package PARAMETER RATING -0.3 to +7.0 -0.3 to (VCC + 0.3) 10 -65 to +125 -55 to +108 UNITS V V mA C C C/W

June 17, 1993

853-1708 10044

BLOCK DIAGRAM

OUT Q D Q D Q D Q Q D Q D Q Q D Q D Q D Q MC IN IN
DC ELECTRICAL CHARACTERISTICS
SYMBOL VCC ICC VOH VOL VIH VIL VIH VIL IIH IIL IIH IIL PARAMETER Power supply voltage range Supply current Output high level Output low level MC input high threshold MC input low threshold SW input high threshold SW input low threshold MC input high current MC input low current SW input high current SW input low current
The following DC specifications are valid for TA = 25C and VCC = 3.0V; unless otherwise stated. Test circuit Figure 1. TEST CONDITIONS MIN fIN = 1GHz, input level = 0dBm No load IOUT = 1.2mA VCC-1.4 VCC-2.6 2.0 0.3 2.0 0.3 VMC = VCC = 6V VMC = 0V, VCC = 6V VSW = VCC = 6V VSW = 0V, VCC = 6V 0.35 0.VCC 0.8 VCC 0.2.7 4.5 LIMITS TYP MAX 6.0 V mA V V V V V V A A A A UNITS
AC ELECTRICAL CHARACTERISTICS
SYMBOL VIN fIN RID VO tS tH tPD PARAMETER Input signal amplitude1 Input signal frequency Differential input resistance Output voltage Modulus set-up time1 Modulus hold time1 Propagation time
The following AC specifications are valid for VCC = 3.0V, fIN = 1GHz, input level = 0dBm, TA = 25C; unless otherwise stated. Test circuit Fig. 1. TEST CONDITIONS MIN 1000pF input coupling Direct coupled input2 1000pF input coupling DC measurement VCC = 5.0V VCC = 3.0V 5 1.6 1.0.LIMITS TYP MAX 2.0 1.1 1.1 VP-P GHz GHz k VP-P VP-P ns ns ns UNITS
NOTES: 1. Maximum limit is not tested, however, it is guaranteed by design and characterization. 2. For fIN < 50MHz, minimum input slew rate of 32V/s is required.

DESCRIPTION OF OPERATION

The SA701 comprises a frequency divider circuit implemented using a divide by 4 or 5 synchronous prescaler followed by a 5 stage synchronous counter, see BLOCK DIAGRAM. The normal operating mode is for SW (Modulus Set Switch) input to be set low and MC (Modulus Control) input to be set high in which case the circuit comprises a divide by 128. For divide by 129 the MC signal is forced low, causing the prescaler circuit to switch into divide by 5 operation for the last cycle of the synchronous counter. Similarly, for divide by 64 and 65 the SA701 will generate those respective moduli with the SW signal forced high, in which the fourth stage of the synchronous divider is

bypassed. A truth table for the modulus values is given below:

Table 1.

Modulus MC SW 1 1
the input. The rising edge of the output occurs at the count 64 for modulus 128/129 or count 32 for modulus 64/65 with delay tPD. The SW input is not designed for synchronous switching. The MC and SW inputs are TTL compatible threshold inputs operating at a reduced input current. CMOS and low voltage interface capability are allowed. The SW input has an internal pull-down simplifying modulus group selection. With SW open the divide by 128/129 mode is selected and with SW connected to VCC divide by 64/65 is selected. The prescaler input is differential and ECL compatible. The output is single-ended ECL compatible.
For minimization of propagation delay effects, the second divider circuit is synchronous to the divide by 4/5 stage output. The prescaler input is positive edge sensitive, and the output at the final count is a falling edge with propagation delay tPD relative to
AC TIMING CHARACTERISTICS

COUNT IN

tS SW = 0. DIVIDE BY 128/129 OPERATION.

COUNT IN 129 1

tS SW = 1. DIVIDE BY 64/65 OPERATION.

COUNT IN 65 1

C1 1000pF

C2 1000pF

SW C3 0.1F

R3 2.2k

C4 5pF
Figure 1. SA701 Test Circuit
FREQUENCY (MHz) 5 MINIMUM INPUT POWER (dBm) 1200
10 40C VCC = 3.0V 20 25C 85C
Figure 2. Minimum Input Power vs Frequency and Temperature
FREQUENCY (MHz) 5 MINIMUM INPUT POWER (dBm) TA = 25C 40 2.7V 3.0V 6.0V 1200
Figure 3. Minimum Input Power vs Frequency and VCC

6 85C 5.5

25C 5 ICC (mA)

4.5 40C 4

3 2.VCC (V) 6 7
Figure 4. Supply Current vs Supply Voltage and Temperature With No Load
VCC = 3V j0.2 j5 TA = 25C

L4 6nH

300 j0.j5

C2 0.4pF

R1 3000

C1 0.9pF

EQUIVALENT INPUT IMPEDANCE 900
Figure 5. Typical N Package Input Impedance

VCC = 3V TA = 25C L4 3nH

C2 0.2pF 300 j0.j5
EQUIVALENT INPUT IMPEDANCE 900 j2
Figure 6. Typical D Package Input Impedance
This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.

 

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